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Journal ArticleDOI

Task Scheduling on the PASM Parallel Processing System

TLDR
The use of multiple FIFO queues for nonpreemptive task scheduling is described and four multiple-queue scheduling algorithms with different placement policies are presented and applied to the PASM parallel processing system.
Abstract
PASM is a proposed large-scale distributed/parallel processing system which can be partitioned into independent SIMD/MIMD machines of various sizes. One design problem for systems such as PASM is task scheduling. The use of multiple FIFO queues for nonpreemptive task scheduling is described. Four multiple-queue scheduling algorithms with different placement policies are presented and applied to the PASM parallel processing system. Simulation of a queueing network model is used to compare the performance of the algorithms. Their performance is also considered in the case where there are faulty control units and processors. The multiple-queue scheduling algorithms can be adapted for inclusion in other multiple-SIMD and partitionable SIMD/MIMD systems that use similar types of interconnection networks to those being considered for PASM.

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Citations
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Journal ArticleDOI

Scheduling in multiprogrammed parallel systems

TL;DR: A preliminary investigation of a number of fundamental issues which are important in the context of scheduling concurrent jobs on multiprogrammed parallel systems to gain insight into system behaviour and understand the basic principles underlying the performance of scheduling strategies in such parallel systems.
Journal ArticleDOI

Distributed hierarchical control for parallel processing

TL;DR: A description is given of a novel design, using a hierarchy of controllers, that effectively controls a multiuser, multiprogrammed parallel system that allows dynamic repartitioning according to changing job requirements.
Patent

Dynamically partitionable parallel processors

TL;DR: In this article, a system for dynamically partitioning processors in a multiprocessor system intercoupled by a network utilizes, in association with each processor, a network accessible, locally changeable memory section.
Journal ArticleDOI

Evaluation of Design Choices for Gang Scheduling Using Distributed Hierarchical Control

TL;DR: It is shown that in DHC this effect can be reduced by reclaiming the leftover processors when the gang size is smaller than the allocated block of processors, and by adjusting the scheduling time quantum to control the adverse effect of badly matched gangs.
References
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Journal ArticleDOI

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TL;DR: This paper discusses the design of a primary memory system for an array processor which allows parallel, conflict-free access to various slices of data, and subsequent alignment of these data for processing, and a network based on Stone's shuffle-exchange operation is presented.
Journal ArticleDOI

Very high-speed computing systems

TL;DR: In this paper, the authors classified very high-speed computers as follows: 1) Single Instruction Stream-Single Data Stream (SISD) 2) SIMD 3) MIMD 4) MISD-MIMD.
Book

Operating Systems Theory

TL;DR: As one of the part of book categories, operating systems theory always becomes the most wanted book.
Journal ArticleDOI

The ILLIAC IV Computer

TL;DR: The structure of ILLIAC IV, a parallel-array computer containing 256 processing elements, is described, special features include multiarray processing, multiprecision arithmetic, and fast data-routing interconnections.
Journal ArticleDOI

The Indirect Binary n-Cube Microprocessor Array

TL;DR: This paper explores the possibility of using a large-scale array of microprocessors as a computational facility for the execution of massive numerical computations with a high degree of parallelism.