Patent
Thermal interface for a printed wiring board
TLDR
In this paper, a printed wiring board is comprised of a combination of layers providing a good thermal match with surface mount components, and an integral thermal interface region is used to dissipate the heat from the core.Abstract:
A printed wiring board is comprised of a combination of layers providing a good thermal match with surface mount components. The board consists of a core surrounded by multiple layers of dielectric and conductive materials optimized for their thermal expansion qualities. The core is also used as a heat sink for drawing excess heat from the components. An integral thermal interface region is used to dissipate the heat from the core.read more
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Patent
Multi-layered interconnect structure using liquid crystalline polymer dielectric
TL;DR: In this paper, a multi-layered interconnect structure and method of formation is presented, in which first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to the opposing surface of a thermally conductive layer.
Patent
Multilayer printed circuit board and method for fabricating same
Tsukada Yutaka,Shuhei Tsuchida +1 more
TL;DR: In this paper, a multilayer printed circuit board and a corresponding fabrication method are disclosed, which circuit board achieves a relatively high degree of wiring density and wiring design freedom, which is obtained in the inventive printed circuit boards by electrically connecting power conductors or ground conductors using through holes.
Patent
Method for interconnecting a stack of integrated circuits at a very high density
TL;DR: In this paper, an integrated circuit (16) is fabricated with a plurality of substrates (50 or 400 or 500) where each substrate has metal edge contact sites (12 or 507) and an interconnect pattern (250 or 423) electrically connects integrated circuits on different substrates.
Patent
System and method for reinforcing a bond pad
Mukil Saran,Charles A. Martin +1 more
TL;DR: A reinforcing system for a bond which includes at least one dielectric layer or stack disposed under the bond pad is defined in this article, where the delectric filling the portion of the patterned structure from which the structure was removed after patterning.
Patent
High density interconnect with high volumetric efficiency
TL;DR: In this article, an interconnect pattern (250 or 423) electrically connects integrated circuits (16) on different substrates, which is removed whenever a substrate is replaced, is reapplied after the removed substrate has been replaced.
References
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Patent
Integrated circuit package with thermal path layers incorporating staggered thermal vias
Marco K. Kuo,Nirmal Sharma +1 more
TL;DR: In this paper, the thermal path layers, the thermal vias and other thermal path elements are fabricated from the same set of materials used in the cavity-defining layers, electrical vias, and conductive strips.
Patent
Multilayer ceramic circuit board
TL;DR: In this article, a multilayer ceramic circuit board and the method of forming such circuit board are disclosed, and the wiring pattern for the multillayer circuit board includes multiple layer portions, the multiple-layer portions including first and second electrically conductive layers, respectively a tungsten layer and a copper thick film.
Patent
Process for manufacturing a ceramic multi-layer substrate
TL;DR: In this article, a multi-layer wire line matrix with a photo-lithographically formed fine conductive pattern is presented, where the metal is plated in and fills the through holes so that the metal not cut off at the corners.
Patent
Heat-removing circuit boards
TL;DR: In this paper, a flat core plate, 1 to 5 mm, of metallic material, graphite or electrically conductive carbon with a coating, 10 to 80 μm thick, of electroplated aluminum eloxal and, optionally, an intermediate layer of copper or silver, 0.1 to 2μm thick.
Patent
A multi-layer circuit board having a large heat dissipation
TL;DR: In this article, a multi-layer circuit board is disclosed which includes a plurality of AlN ceramic layers stocked and combined as an integrated form and wiring layers interposed at different levels between the AlN layers.