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Proceedings ArticleDOI

TMPL: A hardware transactional memory product line

TLDR
The underlying product line development process, TMPL's structure, and an early quantitative evaluation of the FPGA-based implementation of the TMPL implementation are presented.
Abstract
Transactional memory is regarded as a very promising technology to deal with concurrency control in future multicore and manycore systems. While a lot of software, hardware, and hybrid transactional memory implementations have been proposed and analyzed, the silver bullet still hasn't been found. The main reason is that the performance of transactional memory significantly depends on the actual application scenario. TMPL is a product line of transactional memory implementations for configurable hardware platforms, mainly aimed at the domain of embedded systems. It facilitates the derivation of various kinds of transactional memory with a large variety of strategies for conflict detection, conflict resolution, and versioning, from a common platform. Thereby, developers can experiment with different strategies and select one that is most efficient for a given workload profile. This paper presents the underlying product line development process, TMPL's structure, and an early quantitative evaluation of our FPGA-based implementation.

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Citations
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LavA: Model-Driven Development of Configurable MPSoC Hardware Structures for Robots

TL;DR: The LavA framework is described, which facilitates the de- velopment of application-specific MPSoC hardware structures and can interact with Lego Mindstorms NXT sensors and actuators.
References
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ReportDOI

Feature-Oriented Domain Analysis (FODA) Feasibility Study

TL;DR: This report will establish methods for performing a domain analysis and describe the products of the domain analysis process to illustrate the application of domain analysis to a representative class of software systems.
Book

Generative Programming: Methods, Tools, and Applications

TL;DR: This chapter discusses Domain Engineering and Object-Oriented Analysis and Design, and main development steps in Generative Programming, as well as Static versus Dynamic Parameterization, and a Fresh Look at Polymorphism.
Proceedings ArticleDOI

Transactional memory: architectural support for lock-free data structures

TL;DR: Simulation results show that transactional memory matches or outperforms the best known locking techniques for simple benchmarks, even in the absence of priority inversion, convoying, and deadlock.
Proceedings ArticleDOI

STAMP: Stanford Transactional Applications for Multi-Processing

TL;DR: This paper introduces the Stanford Transactional Application for Multi-Processing (STAMP), a comprehensive benchmark suite for evaluating TM systems and uses the suite to evaluate six different TM systems, identify their shortcomings, and motivate further research on their performance characteristics.