Patent
Variable capacity cache memory
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TLDR
In this article, a variable length cache system (58, 60) keeps track of the amount of available space on an output device (10) and the capacity of the cache system is continuously increased so long as it is less than the available output space on the output unit (10).Abstract:
A variable length cache system (58, 60) keeps track of the amount of available space on an output device (10). The capacity of the cache system (60) is continuously increased so long as it is less than the available output space on the output unit (10). Once the size of the cache system exceeds the available output space on the output unit (10), which is less than the total space available on the output unit (10) by a predetermined amount, the contents of the cache memory (60) are flushed or written to the output device (10) and the size of the cache memory (60) is reduced to zero.read more
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References
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Patent
Variable capacity data buffer system
TL;DR: In this article, a data buffer system is provided for controlling the transfer of data between a processor and an input/output (I/O) device and includes a data storage device having a maximum data storage capacity value.
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Cache memory having a variable data block size
TL;DR: In this article, the index is a set associative memory and bits provided to an address input of the index are selectively inhibited by an address inhibit circuit when the size of the data blocks in the data buffer is to be varied.
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Method and apparatus for limiting allocated data-storage space in a data-storage unit
TL;DR: In this article, a data-storage buffer transferring data signals with other units in relatively large blocks of data is made smaller than the data capacity of the large block to more efficiently use the data storage space in the data buffer.
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Stack mechanism with the ability to dynamically alter the size of a stack in a data processing system
Philip E. Stanley,Piotr Szorc +1 more
TL;DR: In a data processing system, a stack mechanism creates a stack of operands in a series of memory locations, and the memory locations are grouped into stack frames corresponding to the operands included within individual procedures executed by a processing unit.
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Arbitral dynamic cache using processor storage
TL;DR: A data cache in a computer operating system that dynamically adapts its size in response to competing demands for processor storage, and exploits the storage cooperatively with other operating system components is discussed in this article.