Patent
Virtualization system using hardware assistance for shadow page table coherence
Keith Adams,Sahil Rihan +1 more
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TLDR
In this article, the authors present a method for maintaining a shadow page table in at least partial correspondence with guest page mappings of a guest computation, marking with a traced write indication at least those entries of the shadow page tables that map physical memory locations which themselves encode the guest page mapping.Abstract:
One embodiment of the present invention includes a method for maintaining a shadow page table in at least partial correspondence with guest page mappings of a guest computation. The method marking with a traced write indication at least those entries of the shadow page table that map physical memory locations which themselves encode the guest page mappings, the marking identifying, for a hardware facility, a subset of memory access targets for which updates are to be recorded in a guest write buffer accessible to the virtualization system. Responsive to a coherency-inducing operation of the guest computation, the method reads from the guest write buffer and introduces corresponding updates into the shadow page table.read more
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Virtual Storage Target Offload Techniques
Jacob Oshins,Dustin L. Green +1 more
TL;DR: In this article, a virtual machine storage service can use a unique network identifier and a SR-IOV compliant device can be used to transport I/O between a VMs and the VMs.
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References
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Proceedings ArticleDOI
A comparison of software and hardware techniques for x86 virtualization
Keith Adams,Ole Agesen +1 more
TL;DR: It is found that the hardware support for Virtual Machine Monitors for x86 fails to provide an unambiguous performance advantage for two primary reasons: first, it offers no support for MMU virtualization; second, it fails to co-exist with existing software techniques for MM U virtualization.
Intel Virtualization Technology : Hardware Support for Efficient Processor Virtualization
TL;DR: Details of the virtualization challenges posed by IA-32 and Itanium processors are provided; an overview and details of VT-x and VT-i are presented; and examples of usage of the VT- x andVT-i architecture are provided.
Patent
Dynamic binary translator with a system and method for updating and maintaining coherency of a translation cache
TL;DR: In this paper, a dynamic binary translator converts input instruction sequences into output instruction sequences that are stored in a translation cache, which is checked by either a conflict detection mechanism or a code-invariance mechanism.
Patent
Enhanced Shadow Page Table Algorithms
TL;DR: In this article, an enhanced shadow page table algorithm is proposed to harmonize the shadow page tables and the guest page tables by using tagged translation lookaside buffers, batched shadow pages table population, lazy flags, and cross-processor shoot downs.
Patent
Deferred shadowing of segment descriptors in a virtual machine monitor for a segmented computer architecture
TL;DR: In this paper, the authors propose a shadow descriptor table that stores shadow descriptors for certain VM segment descriptors, which are then shadowed descriptors are compared with their corresponding shadowed VM descriptors and synchronization for the pair of descriptors is established.
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