VLSI Architecture Design of Guided Filter for 30 Frames/s Full-HD Video

TLDR: To achieve the computation demand of guided filtering in full-HD video, a double integral image architecture for guided filter ASIC design is proposed and a reformation of the guided filter formula is proposed, which can prevent the error resulted from truncation in the fractional part and modify the regularization parameter ε on user's demand.

Abstract: Filtering is widely used in image and video processing for various applications Recently, the guided filter has been proposed and became one of the popular filtering methods In this paper, to achieve the computation demand of guided filtering in full-HD video, a double integral image architecture for guided filter ASIC design is proposed In addition, a reformation of the guided filter formula is proposed, which can prevent the error resulted from truncation in the fractional part and modify the regularization parameter e on user's demand The hardware architecture of the guided image filter is then proposed and can be embedded in mobile devices to achieve real-time HD applications To the best of our knowledge, this paper is also the first ASIC design for guided image filter With a TSMC 90-nm cell library, the design can operate at 100 MHz and support for Full-HD (1920 × 1080) 30 frame/s with 929K gate counts and 32 KB on-chip memory Moreover, for the hardware efficiency, our architecture is also the best compared to other previous works with bilateral filter