Proceedings ArticleDOI
VLSI Design for Testability
Edward J. McCluskey
- pp 2-5
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This article is published in Symposium on VLSI Technology.The article was published on 1984-12-03. It has received 22 citations till now. The article focuses on the topics: Testability & Design for testing.read more
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Patent
Hardware modeling system and method for simulating portions of electrical circuits
TL;DR: In this paper, a hardware modeling system for electrical circuits is presented, which simulates portions of electrical circuits using actual hardware components in the simulation and provides access to these hardware modeling elements on a shared basis to plural workstations.
BookDOI
The evolution of fault-tolerant computing
TL;DR: Experiences in Fault Tolerant Computing, 1947-1971 are explored.
Patent
Circuit verification accessory
TL;DR: In this paper, a hardware modeling system for electrical circuits is presented, which simulates portions of electrical circuits using actual hardware components in the simulation and provides access to these hardware modeling elements on a shared basis to plural workstations.
Proceedings ArticleDOI
Partial scan test for asynchronous circuits illustrated on a DCC error corrector
TL;DR: This work investigates how the partial scan principles from the synchronous test world can be adapted to asynchronous circuits, and shows that asynchronous partial scan design can be approached as a high-level design activity.
Proceedings ArticleDOI
Testability features of the 68040
Michael G. Gallup,William B. Ledbetter,Ralph Mcgarity,S. McMahan,K.C. Scheuer,C.G. Shepard,L. Sood +6 more
TL;DR: The design and implementation of on-chip test functions on the 68040 microprocessor are described, including the global test architecture, special test modes for the internal RAM arrays, the scan circuitry used for structural testing of random logic, and the IEEE 1149.1 (JTAG) implementation on the68040.