Patent
Zero-latency network on chip (noc)
TLDR
Packet format configurability is extended for packets transported on physical links of an Intellectual Property (IP) core interconnect by using at least two independent parameters: one parameter governing data-width and one parameters governing latency penalty.Abstract:
Packet format configurability is extended for packets transported on physical links of an Intellectual Property (IP) core interconnect by using at least two independent parameters: one parameter governing data-width and one parameter governing latency penalty The at least two independent parameters allow creation of transport protocol packets without additional latency insertion, which is useful for low-latency applications The at least two independent parameters also allow creation of narrow packets with multi-cycle additional latency, which is useful for latency tolerant, area sensitive applicationsread more
Citations
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Patent
Heterogeneous channel capacities in an interconnect
TL;DR: In this article, the authors present an example process to construct a heterogeneous channel NoC interconnect, wherein the channel width may be determined based upon the provided specification of bandwidth and latency between various components of the system.
Patent
Co-existence of latency tolerant and low latency communications
TL;DR: In this paper, the presence of both low latency and latency tolerant communications in shared time-frequency resources to try to improve resource utilization is discussed. And in some embodiments, a latency tolerant transmission is postponed to free resources to send a low latency transmission.
Patent
STREAMING BRIDGE DESIGN WITH HOST INTERFACES AND NETWORK ON CHIP (NoC) LAYERS
Rajesh Chopra,Sailesh Kumar +1 more
TL;DR: In this paper, the authors describe a streaming bridge design that helps interconnect and transfer transaction packets between multiple source and destination host interfaces through a Network on Chip (NoC) interconnect, which includes a plurality of NoC router layers and virtual channels connecting the router layers.
Patent
Supporting multicast in NoC interconnect
TL;DR: In this paper, a multicast message from a source component is replicated in the NoC during routing towards the destination components indicated in the message, where one or more multicast trees in the given NoC topology are formed and one of these trees is used for routing a multicasting message to its intended destination components mentioned therein.
Patent
Configurable router for a network on chip (NoC)
Joji Philip,Sailesh Kumar +1 more
TL;DR: In this paper, a configurable building block, such as a router, for implementation of a Network on Chip (NoC) is described. But this router is parameterized by a software layer, which can include the number of virtual channels for a port, number of ports, membership information of the virtual channels, clock domain, and so forth.
References
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Patent
Dynamic robust header compression
TL;DR: In this article, the tradeoff of robustness and reordering depth is discussed for packet reordering over a wireless link, where the compression operation and the decompression operation are dynamically adjusted according to the characteristics of the link.
Patent
Die-to-die interconnect interface and protocol for stacked semiconductor dies
TL;DR: In this article, the authors present a system and method for a die-to-die interconnect interface and protocol for stacked semiconductor dies, which includes an integrated circuit (IC) package comprising a first semiconductor die that includes an interface to a memory-mapped device, a second semiconductor dead that does not include a memory mapped device.
Proceedings ArticleDOI
ParIS: a parameterizable interconnect switch for networks-on-chip
TL;DR: This work presents a parameterizable router architecture for NoCs which is based on a canonical template and on a library of building components offering different alternatives and implementations for the circuits used for packet forwarding in a NoC.
Patent
Generating and merging lookup results to apply multiple features
Bhushan Mangesh Kanekar,Venkateshwar Rao Pullela,Dileep Kumar Devireddy,Gyaneshwar S. Saharia,Dipankar Bhattacharya,Qizhong Chen +5 more
TL;DR: In this article, the authors describe a method for merging lookup results from associative memory banks and/or memory devices, such as access lists and access control lists, to generate a merged lookup result.
Patent
Network-on-chip environment and method for reduction of latency
TL;DR: In this article, the authors proposed an integrated circuit comprising a plurality of processing modules (21, 23, M, S; IP) and a network (NoC) arranged for coupling processing modules, where the data transmission between processing modules operates based on time division multiple access (TDMA) using time slots.