Showing papers on "AND gate published in 1969"

An Algorithm for NAND Decomposition Under Network Constraints

Abstract: A branch-and-bound algorithm is presented for the synthesis of multioutput, multilevel, cycle-free NAND networks to realize an arbitrary given set of partially or completely specified combinational switching functions. In a programmed version of the algorithm, fan-in, fan-out, and level constraints may be specified. Cost may be specified as a nonnegative integer linear combination of gates and gate inputs. Further constraints and cost criteria are compatible with the algorithm. A first solution is constructed by a sequence of local decisions, and backtracking is executed to find improved solutions and to prove the optimality of the final solution.

Prestored area correlation tracker

Abstract: A novel prestored area correlation tracker comprising multiple concentric field of view apparatus in combination with apparatus for memorizing multiple digital representations of a target scene and logic apparatus to utilize such representations for the purpose of recognizing said target scene and accurately maintaining a desired aim point in the scene. A primary embodiment utilizes a small field of view apparatus in conjunction with self made direct view memories for tracking the target scene during range closure, and a large field of view apparatus in conjunction with the previously stored memories for initial pointing and intermediate corrections of the afore-mentioned tracking, with said small field of view tracking minimizing the number of prestored memories required for intermediate corrections.

Count comparison circuit

Abstract: Disclosed is a count comparison circuit for use in artillary fuze timers and the like. The comparison circuit comprises a counting register and a storage register. The complement of the number to be detected is stored in the storage register. OR gates are coupled to the corresponding stages of the registers and when the count is reached the OR gates activate and AND gate to produce an electrical output.

An introduction to threshold logic: a survey of present theory and practice

Abstract: The familiar logic building blocks of AND, OR, NAND, and NOR functions are practical realizations of well-known basic boolean algebraic connectives, and as such enable any two-state logic system to be constructed. however, a more powerful basic logic building block than boolean gates is the `threshold gate?. such a gate has binary inputs A, B, C,?, with `weights? a, b, c,?associated with these respective inputs, and a binary output z. the output from such a gate is: Z = 1 if ?a.A + b.B + c. C +???some value t1 Z = 0 if ?a.A + b.B + c.C +?? some value t2 where normal arithmetic rules are involved in the above summations. such gates can be used to realize all the normal basic binary logic functions, and in addition can realize more complex switching functions which would otherwise require the use of several normal logic gates. thus the number of gates in a switching system may be drastically reduced by using threshold gates in place of the normal types.

An Automatic Sorting System

Abstract: 1,168,509. Sorting postal mail; labels. M. CAMBORNAC, J. CHAZOT, and L. PUECHBERTY. 14 June, 1967 [19 May, 1967], No. 27551/67. Headings B8A and B8F. [Also in Divisions B7 and H4] In an automatic sorting system for mailbags 11, Fig. 5, or like articles, being conveyed upon a conveyer 60, labels 10 are attached to said mailbags which have surfaces upon which particulars of the destinations of the mailbags are written, and which contain radio apparatus for receiving a signal from an interrogating station and for transmitting a characteristically coded reply, using power received from the said interrogating station. As described, an interrogating station ahead of a branching place 62 is provided with an enclosure 50 containing a transmitter and a receiver which are activated only when a mailbag passes by and obscures a light beam 521- 522 directed upon a photo-electric cell. Power radiated by an aerial 511 is received by the apparatus in the label 10, from which a reply is received by an aerial 531. A label may be approximately 6 cm. by 12 cm. and comprise a plate carrying on one face miniaturized or integrated electronic circuit components which are embedded in plastics material, and providing on the other face a surface for a written address. It may comprise a female connector 80, Fig. 3, into which may be inserted an interchangeable key 90, Fig. 3a, for setting up a particular code. In one embodiment the responder circuit of a label comprises an aerial 211, Fig. 7, coupled to an inductor 212 which resonates with a capacitor 213 at the frequency F of the interrogating transmitter. A capacitor 222 is charged through a diode 221 when a signal is received and power is supplied to an R.F. oscillator 23, comprising a PNP transistor 234, and to ten modulating oscillators 240-249 comprising NPN transistors 2400-2490. An aerial 231 is coupled to an inductor 232 in the oscillator 23 which resonates with a capacitor 233 at the response carrier frequency f of the label circuit. The modulating oscillators comprise resistance/ capacity phase shifting networks and oscillate at different intermediate frequencies Ifo to Ifg. Their outputs may be coupled to the oscillator 23 by connectors 200-209, which may be provided by the key 90, Fig. 3a. With ten modulating frequencies available 2 10 , or 1024, codings are possible. In a second embodiment, the label circuit is arranged to divide the response time into ten intervals, and is provided with means for transmitting on two frequencise, f 1 and f 2 . During the first interval a start signal (f 1 only) is returned to the interrogating station and during the remaining nine, a code signal (f 2 in all, plus f 1 in four), 126 combinations being available. A capacitor 222, Fig. 9, supplies power to a resistance/capacity coupled oscillator 240 producing rectangular waves, a ring counter 71 with decoder 72, and to two oscillators 23, 23 1 having respective aerials 231, 231 1 from which response signals at frequencies f 1 f 2 may be radiated. The oscillator 23 is controlled by an AND gate 74 with inputs from the oscillator 240 and an OR gate 73. The oscillator 23 1 is controlled by an AND gate 75 with an input from the oscillator 240 and an inverted input from the output " 0 " of the decoder 72. The OR gate 73 has one input from the output " 0 " of the decoder 72, and another from a terminal which is connected to a tooth on the key 90 when it is inserted. The key 90 is also connected by coding teeth via terminals and diodes to selected ones of the outputs 1-9 of the counter 71 and decoder 72. When the interrogating signal is received the counter 71 is at zero, and the negative half wave from the oscillator opens the gate 74 and closes the gate 75 so that the oscillator 23 sends the start signal (f 1 ) There after, as the counter 71 is stepped, the gate 75 is opened at each of the remaining nine intervals so that the oscillator 231 sends a signal at the frequency f 2 . The gate 74 is only opened when at a particular step a tooth on the key 90 has been provided, so that an impulse is transmitted via the key to the OR gate 73, and thence to the said gate 74, when the oscillator 23 sends a signal at the frequency f 1 . At the interrogating station (Fig. 10, not shown) two separate receiving means are provided, one tuned to the frequency f 1 and the other to the frequency f 2 . Their outputs operate a decoder via circuit arrangements including a shift register and a counter. A detector for the passage of a mailbag controls the two receiving means and resets the shift register and the counter. In a third embodiment, a common carrier frequency F is used for interrogation and response, and signals from the fixed station are modulated at a clock frequency JH. A detector 52, Fig. 12, at the fixed station triggers a programmer 120 when a mailbag arrives so that a clock frequency oscillator 128 generates a train of ten pulses which modulate a transmission at carrier frequency from a transmitter-receiver 122 and also cause a ring distributor 125 to advance step by step. At the label, the modulated wave is received by a transmitter-receiver 112, Fig. 11, is detected by a detector 113, is separated into stepping pulses and a feed voltage by filters 114, 115, and is applied to a ring counter 116. This successively feeds the ten terminals of a connector 117, in which is inserted a key 90 having teeth according to the coding appropriate to the mainlbag. Where there is a tooth, a voltage is passed back to the transmitter-receiver 112 which operates a variable reactance element, e.g. a diode, in the oscillatory circuit thereof, and modulates the retransmitted wave of frequency F. At the fixed station, signals received by the transmitter-receiver 122, Fig. 12, are demodulated and detected and applied to the input of the ring distributor 125. The signals are thus successively directed towards each of ten trigger circuits of a register 126, and those which are modulated as a result of the label coding operate a decoder 127.

High-speed parallel binary adder

Abstract: There is described a parallel adder for operands of 48 bits in which the carry information is generated simultaneously for all orders. The carry logic, consisting entirely of AND gates, is arranged in three levels. The adder consists of independent subadders of four orders each. The carry logic and subadders combine to form a maximum of four cascaded gate levels for generating the sum of any order of bits. Duplicate true and false logic is used at all levels. The second and third levels of the carry logic are arranged in an interleaved configuration to limit fanning.

Hit detection shock system

Abstract: A hit detection system comprising energy-sensitive detectors arranged in an array over a target area of interest. Each detector is connected to a separate amplifier whose output is connected to the input stage of a separate shift register through a threshold circuit. The shift registers are clocked simultaneously by clock pulses from a synchronized clock, the clock pulse period being a function of the time required for energy to traverse a distance which equals the dimension of a hit location area of interest. For each hit location area of interest an AND gate is included. The inputs of each gate are connected to selected stages of the shift register so that only when an impact occurs in the hit location area, associated with the gate, does the latter provide a hit-indicating output.

Solenoid error checking system

Abstract: 1,246,765. Checking circuits. NATIONAL CASH REGISTER CO. 9 March, 1970 [24 March, 1969], No. 11065/70. Heading G4H. A circuit for checking that one and only one of an array of solenoids 12 is energized comprises a sensing circuit 28 having an output 30 on which a signal appears when at least one of the solenoids has been energized and an output 32 on which an error signal appears when at least two of the solenoids have been energized and a logical circuit to which is applied the energization signal on terminal 10 and the output 30 is applied, the logical circuit being arranged to provide a further error output 32 if an energization signal appears in the absence of a signal at 30 or vice versa. One of the solenoids 12 is selected by a circuit 14 controlled by an input at 16. When the energization pulse is applied to terminal 10 the selected solenoid is energized through a silicon controlled rectifier. The energization pulse is also applied via one-shot circuit 22 to set flip-flop 24, and via an inverter 18 to gates 20 and 40. Sensing circuit 28 has input terminals 42, 44, 46, each coupled to one of the solenoids. The output 30 indicating that at least one solenoid has been energized is applied to the reset input of flipflop 24, to input 37 of gate 40 and to one-shot circuit 36 connected to circuit 38 resetting circuit 28. The reset output of flip-flop 24 is coupled to gate 20. Output 32 and the outputs of gates 20 and 40 are connected through an Or gate 34 giving an error signal on terminal 47. In normal operation the energization pulse causes one solenoid only to be set, so that there is an output at 30 but not at 32. The energization pulse is inverted to give a "0" at inputs 21 and 35 of gates 20 and 40 which are thereby blocked and no signal passes to Or gate 34. If no solenoid is energized in response to an energization pulse, the flip-flop 24 is set by the pulse and it remains set since no reset signal is applied from terminal 30. At the end of the energization pulse, therefore, the ouptut of the inverter 18 becomes "1" and gate 20 gives an output to Or gate 34. If a solenoid is energized in the absence of an energization pulse both inputs to gate 40 are "1" and an error output is produced. If two or more solenoids are energized, an error signal is produced at 3. The sensing circuit 28 (Fig. 2, not shown) comprises a capacitor for each solenoid. The capacitor is normally charged and is discharged as a result of the firing of the SCR to energize the solenoid. Current is drawn through a resistor providing a voltage drop which is applied to two transistors. One responds when only one solenoid is energized and both respond if two or more are energized. The resetting signal from circuit 38 re-charges the capacitors ready for the next cycle.

Circuit for detecting a change in voltage level in either sense

Abstract: First and second cross-coupled logic gates respectively connected to third and fourth logic gates, with feedback connections from the third to the second and the fourth to the first gate. The input voltage level whose change in value it is desired to sense is applied to the third gate and its complement is applied to the second and fourth gates. When this input voltage changes its value in one sense, an output pulse is produced by the third gate and when it changes its value in the opposite sense, an output pulse is produced by the fourth gate. The logic gates may be NAND or NOR gates.

Digital to analog translator

Abstract: A translator comprises a plurality of AND gates. Each AND gate has an input for a binary and a sampling signal. Upon receipt of a binary signal and sampling signal by one of the AND gates a capacitor is charged to the voltage of the sampling signal. Thereafter, that capacitor and other similarly charged capacitors are summed through a logical OR gate. The capacitors have values in proportion to the coded digital input. The logical OR gate in turn is tied to an output transistor which provides a signal which is the analog equivalent of the binary-coded number received at the AND gates.

Improvements in or relating to vehicle guidance systems

Abstract: 1,259,720. Leader gear systems. MOBILITY SYSTEMS Inc. 19 Dec., 1969, No. 61962/69. Heading H4U. [Also in Division G3] A vehicle 10, Fig. 1, proceeding along a guidance path 12 in response to sensors in the vehicle, receives from an encoder 20 a signal indicating that it is approaching a position with respect to a decision point 16 from which it must start a programmed path 18 to intercept a guidance path 14 along which it is to proceed. The circuitry carried by the vehicle 10, Fig. 2, comprises a guidance path steering control and a programmed path steering control. The guidance path steering control comprises sensors 30 for detecting the guide path the output of which is fed, through a normally open gate 32, to an amplifier 34 energizing a motor 36 positioning the steering mechanism 38. A signal from the encoder 20, Fig. 1, is detected by a command box 65 and sets a binary device 66 the true output of which is applied to an AND gate 64. The gate 64, when enabled by a binary device 63, opens a gate 46 to feed a programme signal from an amplifier 45 to the amplifier 34, opens a gate 51 to feed a feedback signal from a transducer 50 to the amplifier and, through an inverter 67, closes the gate 32. The vehicle is thereby caused to transfer to a programmed curvilinear path to the intersecting guidance path. The programmed path steering control comprises an eight-position shift register 40 having function generators F1-F8 providing steering signals representative of successive areas of the programmed path, which is stepped at incremental distances, by a signal from a wheelturning decoder 70 through a gate 71, opened by the signal from gate 64 and a select gate 61. The programme in shift register 40, or an alternative in a shift register 41, is selected by a signal from a command box 60 enabling the appropriate gate 61, 62. The command box 60 simultaneously sets the device 63 to enable the gate 64. On completion of the programme a signal from the last stage of the selected shift register resets binary devices 66, 63 whereby the gate 32 is closed and gates 51, 54 opened restoring the control of the steering mechanism to the guidance sensors 30.

Field effect transistor as a buffer for a small signal circuit

Abstract: A field effect transistor having its drain and gate electrodes connected across a large signal generator and its source and gate electrodes connected across the input of a small signal circuit for protecting the circuit from high level signal variations at the generator.

Asynchronous binary array divider

Abstract: This invention comprises an asynchronous binary divider which incorporates a plurality of subtractors connected in such a manner as to shift the difference from one operation to the next. The information flows through the divider with the results appearing at the output without the need for a clock. The divider of this invention uses a plurality of subtractors which receive the divisor and subtract it from the dividend and subsequent remainders. A generated borrow from the most significant digit of the first subtractor indicates whether or not the dividend is larger than the divisor. The individual bits of the remainder generated by the first subtraction are fed to logic circuits comprising a pair of AND gates and an OR gate, and the outputs from the logic circuits determine the values applied to the next row of subtractors. The remainder generated by each successful subtraction is used as the minuend for the next, the divisor is used as the subtrahend for each subtraction and the inverted borrow from the most significant bit of each subtractor serves as the quotient digit in each subtraction row. The remainders at the end of the operation consists of the outputs from the final logic circuits.

Parallel signal logic comparison circuit

Abstract: A logic circuit to effect the comparison of a number m of lines in a set of n lines A and energized in any sequence with a number q of energized lines in a set of p lines B. A matrix has a series of n inputs linked to the n row lines and a series of p inputs linked to p column lines. At the nodes of the row and column lines, an AND gate is provided having an inverted output. The inverted output is connected to one input each of two AND gates each having another input supplied by the respective row or column line to provide an output from the row or column line at the nodal point if, and only if there is no coincidence of input. The row and column lines are connected to OR gates and to a comparator, energization of the row or column OR gate, respectively, indicating that the larger number of row or column lines was energized initially; if both OR gates are deenergized, the comparator will indicate equality of numbers of input lines energized.

Flueric self-biasing and gate

Abstract: A flueric AND logic element is disclosed which is capable of accurate and reliable operation without the necessity of critical dimensional control. This is accomplished by the use of a pair of fluid bias channels which produce a low pressure region in the vicinity of the control nozzle. In one embodiment the bias channels are located between the two input signals and the two control channels of the respective amplifiers. In a second embodiment both bias channels feed into a central control channel located between the two interaction chambers of the respective amplifiers.

Fail-safe pulsed logic and gate

Abstract: A DC logic handling fail-safe pulsed logic AND gate circuit capable of warning the user whenever substantially any single catastrophic component failure occurs inhibiting any of the functions a DC logic circuit is required to perform. It is a multiple input AND gate circuit with the inputs repeatedly pulsed to develop a resulting pulsed output when no input signals are inhibited and there are no circuit disorders within the gate circuit. Biasing circuits within the gate circuit are so subject to bias voltage variation with a signal input inhibit or internal circuit disorder as to inhibit the pulse signal output and thereby warn.

An Analogue-To-Digital Converter

Abstract: 1,154,795. A/D converters. SOLARTRON ELECTRONIC GROUP Ltd. 16 Jan., 1968 [17 Jan., 1967], No. 2486/67. Heading G4H. After an analogue to digital converter operated in discrete steps has digitized an analogue voltage to the nearest unit (e.g. as in Specification 950,647), a remainder voltage of less than one unit being indeterminate, a signal Vi, Fig. 1, the final value of which differs from the initial value by an amount which represents the remainder voltage, is fed to comparator 10, the output 3 from which controls a gate 12 through which a pulse is fed to a counter or integrator 11 (connected to the other input 2 of the comparator) whenever the comparator inputs differ by a predetermined amount. The stepped voltage V 0 fed to the comparator may be differentiated or passed through a blocking capacitor so that a pulse train representing the remainder voltage is obtained. Where the input Vi to the comparator may decrease as well as increase a current drain may be connected to one side of the integrator (Fig. 3, not shown). Alternatively separate comparators 30a, 30b (Fig. 5) may be used when the voltage is increasing or decreasing, AND gates 32a, 32b passing positive or negative pulses to the integrator 11 when their associated comparators deliver output signals 3a or 3b. By differentiating the integrator output signal V 0 positive and negative output pulses representing increasing and decreasing values of V i may be obtained. In the embodiment of Fig. 6 (not shown) the output pulses from the gate (12) are accumulated positively in a reversible binary counter (21) controlling a D/A converter (22) the output signal V 0 from which is fed to the comparator. A clock pulse generator (24) counts the binary counter (21) downwards. The output pulses (VP) passing through the gate (12) represent the remainder voltage (Vi), the clock pulse generator (24) providing a zero offset to the converter. In a modification the comparator may be replaced by two comparators and two associated gates, the output from one of the gates counting the binary counter upwards and the output from the other counting it down.

Telephone switching translator

Abstract: Gate circuits are allocated to the evaluating circuits in the evaluating translator unit. These gate circuits are provided with current via low-resistance secondary paths before evaluation. The gates circuits are connected to the outputs of a counting chain adapted to block the low-resistance secondary paths of the gate circuits, individually in succession, for the purposes of evaluation. The interrogation of the translator outputs involves no significant new building up processes, since only one translator output loads the corresponding row resistor at a time. Further gate circuits are assigned to the evaluating circuits. The pulse responsible for indexing the counting chain is fed, via a time-lag component, to these gate circuits. This measure ensures that no invalid output information is indicated during the short period before the occurrence of blocking.

Lighting control apparatus

Abstract: 1,171,914. Lighting control systems. THORN ELECTRONICS Ltd. 19 Oct., 1967 [21 Oct., 1966], No. 47340/66. Heading H2H. [Also in Division G3] The Specification relates to lighting control systems generally similar to those described in co-pending Specifications 1,171,915 and 1,171,916, but is primarily directed to the layout and functioning of the channel selector and the input scanner. As shown, the selector 13 comprises a " hundreds " register 50 and a " tens " register 51, both of which can be set by push-buttons (not shown) and which are connected to corresponding AND gates in respective matrices 52, 53, each gate also receiving an input from the corresponding " hundreds " and " tens " outputs of the divider circuit 16. The output 54, 55 of the matrices are connected to an AND gate 56 in turn connected to all the AND gates in the matrix 58 of the input scanner 22, each of the latter gates also receiving an input from a fader and an input from the unit register of the divider 16. Thus the fader outputs appear at terminal 59 for the range of channels selected by selector 13, the matrix 58 being duplicated to provide two output terminals respectively supplying " raise " and " dim " analogue signals from the faders. The channel selector may be modified according to the number of faders provided in the system, e.g. the channel selector may have " hundreds," " tens " and " units " if only one fader is present. Operation of the system for various numbers of faders is discussed. If a greater number of channels are required, the divider and channel selector are modified together with an increase in the master oscillator frequency or the time of the divider cycle. The Specification also describes an AND gate matrix, Fig. 4 (not shown), suitable for the file selector (35) of the lighting control system of Specification 1,171,916.

Improvements in Control Circuits for Static Convertors

Abstract: 1,170,248. Converting. ENGLISH ELECTRIC CO. Ltd. 4 May, 1967 [6 May, 1966], No. 20279/66. Heading H2F. [Also in Division G3] In a circuit for controlling the conduction angle of controlled rectifiers in a converter, a sawtooth voltage is developed, the slope or frequency of which is dependent on the error between the required and actual output of the converter, firing pulses being developed from the sawtooth voltage so as to reduce said error and a control circuit for ensuring that the firing angle is within predetermined minimum and maximum limits. The invention is applicable to control of a three-phase bridge (Fig. 1, not shown) of mercury pool or thyristor rectifiers in an HVDC transmission system or in a D.C. motor control system for a rolling mill. The controlled quantity may be D.C. voltage, current or power; A.C. power or phase angle or speed of a D.C. motor. As shown in Fig. 2, the upper and lower limits of the firing angle a are determined in blocks 15 to which is fed a sine wave derived from the A.C. side which is delayed at 35 by 5 degrees then squared at 36 and differentiated at 37 to provide positive pulses corresponding to the desired minimum firing angle. These pulses trigger a bi-stable circuit 38, the output of which is fed to an AND circuit 39. The input sine wave is also fed to a phase reversal circuit 41 followed by a 10 degrees advance at 42 before being squared at 43 and differentiated at 44, the resulting positive pulses occurring at the desired maximum firing angle and are fed to AND circuit 39. A D.C. amplifier 19 determines the difference between the actual output and the required output (as set on potentiometer 20) and control the rate of rise of output voltage of a Miller integrator 21. When the output of integrator 21 reaches a threshold level, bi-stable circuit 22 is triggered so as to allow the AND gate 23 to pass the output of bi-stable circuit 38 via an OR circuit 24 to a pulse generator 25, 26, the output of which resets the integrator 21 and is distributed by a ring counter 16 and OR circuit 46 to the control electrodes of the six main rectifiers. The firing angle is thus determined by the slope of the output from integrator 21 (or frequency of pulses derived therefrom) which in turn depends on the error between required and actual output quantities. A separate control circuit 15 is provided for each main converting element, co-operating with a single firing pulse generator 14 which thus operates at six times the supply frequency when employed with a three-phase bridge system. Minimum firing angle.-If potentiometer 20 is set so as to demand a converter output greater than its maximum, the output from integrator 21 rises rapidly to its threshold value and allows AND gate 23 to pass a pulse at the time of the minimum firing angle (5 degrees). Integrator 21 is thus reset at this time. Maximum firing angle.-If potentiometer 20 is set in an attempt to provide an exceptionally low output (e.g. when operating as an inverter), the output from amplifier 19 is so low that the output from integrator 21 never reaches the threshold imposed by bi-stable circuit 22. The AND circuit 23 is thus never opened and a firing pulse is developed from the maximum firing angle pulse produced in circuit 44. This pulse is fed via OR circuit 24 to trigger the main converting elements and to reset integrator 21.

Band-limited fm detector

Abstract: The output IF signal of an FM receiver is coupled to an AND gate and also used to actuate a timer. The timer output is coupled to a second input of the AND gate and the initial output of the timer enables the AND gate for a fixed predetermined time period. The initial portion of the IF signal disables the AND gate while the terminal portion of each cycle of the IF signal enables the AND gate. The AND gate puts out a signal consisting of a series of pulses which are filtered or integrated to develop an output signal, which is a linear function of the frequency over the band of the FM detector.

Reversible Electrical Code Converter

Abstract: 1,150,675. Reversible code converters. NIPPON ELECTRIC CO. Ltd. 1 May, 1967 [4 May, 1966], No. 20058/67. Heading G4H. A reversible electrical code converter comprises a conversion matrix and a gating arrangement having two states, the gating arrangement being such that in one state it primes AND gates G1-G4 (Fig. 1) to enable coded signals in a first code X to be converted into a second code Y 1 and in its second state it enables AND gates G5-G8 to enable coded signals in the second code to be converted back to the first code. A two-bit coded signal (0, 1) in the first code X fed to bi-stable devices F1, F2 results in a four-bit output signal from the bi-stable devices which is fed through the gates G1-G4 primed by the output of bi-stable device F3 and amplifier inverters A1-A4 having output signals 0, 1, 1, 0 respectively to the diode conversion matrix to give an output signal only on line 7. This results in diodes D11, D16 conducting to give output signals on lines 9, 11. These lines are not however connected to OR gates G11, G12 so zero signals are applied to inverter amplifiers A11 A12 to give an output code (1, 1) on the terminals 29, 30. In a similar manner if the code (1, 1) is applied to the input terminals 25, 26 the original signal (1, 0) is obtained at the terminals 27, 28.

Improvements in or relating to Digital-to-Analogue Signal Converters.

Abstract: 1,154,092. Digital/analogue converters. MARCONI CO. Ltd. 22 Feb., 1968 [4 May, 1967], No. 20873/67. Heading G4H. Clock pulses on parallel leads, the width of the pulses being in binary relationship are applied to gates d, c, b, a (Fig. 1) to which are also fed binary coded input signals, the output signals from the gates being combined to give either a width modulated output pulse or a series of pulses, the sum of the widths of which represents the input signal. The output signal may be applied to an averaging network AN which gives a signal, the magnitude of which represents the digital input. The gates may be AND gates (Fig. 1) their outputs being combined in an OR gate or NOR gates (Fig. 2, not shown) in which case the digital input signals are fed in via inverters. Alternatively (Fig. 4, not shown) NAND gates may be Used, the outputs from which are combined in a further NAND gate. The clock pulses are derived from divider circuits A, B, C, D (Fig. 1).

Controlled rectifier with improved switching characteristics

Abstract: This is a continuation of U.S. Pat. No. 641,367 filed May 25, 1967 and now abandoned. This invention relates to a gate controlled PNPN semiconductor device having turnoff capability, and more particularly to a turnoff thyristor having both low current gain characteristics and high reverse gate to cathode emitter voltage characteristics. In this device an emitter region is formed in a base region by diffusion and gate contacts are alloyed through the emitter region to the base region.

Method and apparatus for automatically determining characteristic parameters

Abstract: A method and apparatus for automatically determining the characteristic parameters of a tunnel diode or other device having nonlinear and preferably not monotonic characteristics, that is having a peak or valley in its characteristic curve, is disclosed. A bias voltage is applied to the diode at a level determined by the output of a dependent ramp source, the source being such that on application of an input pulse the applied bias level increases. A 100 Hertz small signal square wave voltage is also applied to the diode and an AND gate determines the phase relationship of that voltage and the resultant square wave current through the diode. The AND gate output triggers the dependent ramp source increasing the applied bias voltage until such a peak or valley point is reached or passed.

Method and apparatus for multiplying analog electrical quantities

Abstract: Apparatus for multiplying analog electrical quantities comprises an integrator, such as a Miller integrator, to whose input can be selectively applied two or more electrical quantities, in the form of positive voltages, or a reference voltage, which is a negative voltage. The output of the integrator is connected to a signal range indicator whose output is connected to the inverted input of an OR gate and to a logical control circuit connected to the output of a start generator. The logical control circuit is connected to the non-inverted input of the OR gate, and the OR gate is connected to one input of an AND gate whose other input has connected thereto a post generator. The output of the AND gate is connected to a counter whose counting direction is controlled by the logical control circuit, and the counter-output is connected to a digital indicator. To multiply the analog electrical quantities, the logical control circuit is activated to apply the first electrical quantity to the integrator and simultaneously to open the AND gate for transmission of a predetermined number of pulses from the pulse generator to the counter counting in the forward direction. After counting of the predetermined number of pulses, the first electrical quantity is disconnected at a first given time and the reference voltage is applied to the integrator while resetting the counter toward zero, until the voltage at the integrator output is zero at a second time. The reference voltage is then disconnected and a second electrical quantity is applied to the integrator while pulses are transmitted to the counter which is still counting in the backward direction, until the counter reading is zero. When the counter reading is zero, the second electrical quantity is disconnected at a third given time, the counter is set to count in the forward direction and the reference voltage is again applied to the integrator while the pulses are transmitted to the counter. The pulse count is then continued until the integrator output voltage is again zero.

Improvements in or relating to Methods of and Apparatus for Testing Encoders and Decoders in P.C.M. Transmission Systems

Abstract: 1,170,448. Testing apparatus for P.C.M. systems. MARCONI CO. Ltd. 3 Feb., 1967 [24 May, 1966], No. 23162/66. Heading G4H. A pulse code modulation system including testing apparatus for the encoder (Fig. 1), or the decoder (Fig. 2), comprises a first detector 6 (Fig. 1), 15 (Fig. 2) for detecting in normal transmission the occurrence of signals of a predetermined level applied to the input of the encoder or decoder, a second detector 5 (Fig. 1), 16 (Fig. 2) for detecting the occurrence of encoder or decoder output signals corresponding to input signals of the predetermined level and means 7 (Fig. 1), 17 (Fig. 2) for producing a fault indicating signal in the event of non- correspondence of the detected signals. In the embodiment described the encoder which is of the type in which the input signal is compared in a comparator 2 (Fig. 1) with a signal from a level synthesizer 3, the output from the comparator being fed to logic circuitry 4 controlling the synthesizer 3, the binary coded output from the comparator 2 is fed through an AND gate 9 enabled by a fault code generator 8 when there is coincidence of signals to the comparator 7. If, however, the level detector 6 gives an output when there is no output from the detector 5, the AND gate 9 is disabled and an error signal is transmitted. At the decoder, in which the binary coded signal transmitted on lead 12 is converted into an analogue signal and transmitted by a gate 19, a fault code detector 18 detects incoming signals corresponding to a fault indicating signal to disable the gate 19. The gate 19 is also disabled when there is non- coincidence of signals to the comparator 17. Multiplexing arrangements may be included at the input 1 (Fig. 1) of the encoder and at the output 20 (Fig. 2) of the decoder.