Showing papers on "AND gate published in 1971"

Threshold logic

Abstract: A threshold gate has binary inputs and outputs just like any other logic gate. The difference, however, is that in the threshold gate the inputs may be weighted and, eventually, a binary decision made as to whether the total weight is more or less than some reference. This principle of weighting and summing the inputs rather than simply noting the presence of all inputs as high (as in an AND gate) or one input high (as in an OR gate) is the reason that a threshold gate can tell more about the state of the inputs, thus providing greater ``logic power.'' This article gives some examples of the applicability of threshold logic, as well as an integrated-circuit approach for building arrays of versatile threshold gates. In addition, some logic designs are described and compared with conventional ECL implementations.

Mosfet logic inverter for integrated circuits

Abstract: The specification discloses a logic inverter comprised of a depletion mode MOSFET used as a resistive load between a drain supply voltage and an output and one or more enhancement mode MOSFET''s connected between output and source supply voltage. The source and gate of the depletion mode device are electrically common, and the gates of the enhancement mode devices form the logic inputs. The use of one enhancement mode device provides a simple inverter, a plurality of enhancement mode devices in parallel form a NOR gate, and a plurality of enhancement mode devices in series form a NAND gate. Combination NOR and NAND GATES may also be formed. The basic inverter circuit is also combined with a push-pull output stage to provide increased speed of operation, particularly at higher drain supply voltages. Still another embodiment utilizes an enhancement mode transistor connected between the depletion mode transistor and the output of the basic inverter stage to provide a disable function in which output drain current is switched off under all logic input conditions.

Detector having a constant false alarm rate and method for providing same

Abstract: A detector which may be subject to temperature variations and power supply drift comprised of an avalanche transistor circuit having a variable threshold that is sensitive to input signals within a useful frequency band and noise which produces threshold signals when the amplitude of the input signals or the noise exceeds the instantaneous value of the variable threshold. The rate at which the threshold signals are produced is determined in an N bit storage device coupled to the avalanche transistor circuit and clocked at a specific repetition rate. The storage device has each stage coupled in parallel to an AND gate and to a summation network. The AND gate produces an output signal which indicates input signals are present when each stage of the storage device applies a specified output signal to the AND gate. The summation network produces a variable output signal having an amplitude that varies at a rate proportional to the rate at which the threshold signals are produced. The variable amplitude signal is applied to a serial circuit which shunts the collector current of the avalanche transistor circuit at a rate commensurate with the rate the variable amplitude signal varies in response to noise but at a substantially lower rate than the rate the variable amplitude signal varies in response to input signals. The serial circuit thereby controls the threshold sensitivity of the avalanche transistor to provide a constant false alarm rate for the apparatus while also compensating for temperature variations and drift in the voltage level of the power supply.

Anti-skid system

Abstract: This relates to an electronic control system for an anti-skid system having one braking pressure control valve actuated by the control system to regulate the braking pressure applied to the wheel brakes of both wheels of one axle of a vehicle. The control system includes a speed sensor associated with each wheel. A reacceleration detector, an incipient skid deceleration detector and a speed decrease detector is coupled to each sensor and a subtractor is coupled to both sensors. A first series circuit including a first AND gate and a first time delay device is coupled to one of the incipient skid deceleration detectors and one of the speed decrease detectors. A second series circuit including a second AND gate and a second time delay device is coupled to the other of the incipient skid deceleration detectors and the other of the speed decrease detectors. First logic circuitry is coupled to each of the time delay devices and the subtractor to produce a first actuation signal for the control valve to release the braking pressure in both wheel brakes when both of the incipient skid deceleration detectors and both of the speed decrease detectors having an output signal or when the subtractor has an output signal, one of the incipient skid deceleration detectors has an output signal and one of the speed decrease detectors has an output signal. Second logic circuitry is coupled to each of the time delay devices and each of the reacceleration detectors to produce a second actuation signal for the control valve to reapply braking pressure to both wheel brakes when both of the reacceleration detectors have an output signal and both of the time delay devices have an output signal, or when one of the time delay devices has had no output signal and the other of the time delay devices has had an output signal and the associated one of the reacceleration detectors has an output signal.

Chroma key circuit

Abstract: A circuit for generating an output pulse upon the occurrence of a selected color in color television signals features a matrix to form two chrominance difference signals. Four variable gain amplifiers multiply the difference signals by the sine and cosine of a control voltage which is a course color control. Two circuits each comprising a summer, inverter, and clamp circuit each add the outputs of two of the multiplied signals. An AND gate combines the output of the summer circuits and also is coupled to a variable bias supply, which is a fine color control. A delay line, a second AND gate, and a clipper and zero reference then shape the output pulse.

Digital sorter and ranker

Abstract: A digital sorter and ranker in which pairs of binary words are subtracted from each other in adders by feed-in in one word of the pair together with the adjacent word one''s complement. A carry output indicates which word is the lowest and this output is fed through coincidence logic circuits to additional series of address and logic circuits in pyramid fashion until a single output is obtained from a final adder. The adder logic circuits, the carry output and the output of the final adder are fed through minimum value logic circuits to a series of minimum value flip-flops with the outputs thereof being fed back to the adders and their logic circuits. To record the rank of each word, a series of flip-flop groups with each group corresponding to a binary word is set according to the word''s rank, the flip-flops being controlled by gating circuits fed by preceding logic circuits, the final adder, and a binary counter.

Binary full adder-subtractors

Abstract: A binary full adder-subtractor includes a first logic circuit which is supplied with binary digital signals respectively corresponding to an operand and an operator; a second logic unit which is supplied with the outputs of the first logic unit and a first carrying or borrowing signal of a preceding digit; and a gating circuit including AND gate circuits and OR gate circuits and which is supplied with binary digital signals respectively corresponding to the operand, the first carrying or borrowing signal, the output of the first logic unit and an operating signal for starting an addition or subtraction operation, to provide a second carrying or borrowing signal for a succeeding digit.

Apparatus for sorting products according to their lengths

Abstract: An electrical apparatus for sorting products according to their lengths. In this apparatus the products are passed through a scanning zone which is provided with a light sensitive cell and a source of illumination arranged so that illumination of the light sensitive cell is interrupted while the product is passing through the scanning zone and an electric pulse is generated while the product is in this zone. This pulse is transmitted from the photocell amplifier to the toggle flip-flop which provides one input to an And gate in the circuit which controls the energization of the solenoid valves controlling the air blasts that deflect the product according to their lengths. This pulse is also transmitted from the photocell amplifier to a signal expanding device which controls a gate between an oscillation generator and an electronic counter so that pulses are transmitted from this generator through this gate to the counter for the duration of the expanded pulse to provide a measure of the product length. The expanded pulse is also supplied to delay circuit to provide a strobe pulse to the logic of this apparatus which supplies three outputs corresponding to the long, medium and short product lengths. These outputs are connected to separate product length flip-flops which are connected to the And gates provided to the circuit controlling the air blast control valves. Each of the And gates have a pair of inputs, one of which is supplied by the output of the toggle flip-flop and the other of which is supplied by the product length flip-flops. Thus, the And gates control which of the air blast solenoid valves is to be energized. If the long product flip-flop supplies a signal to the long product And gate then the long product air blast valve is opened and if the medium or short flip-flop supplies the control signal to the medium or short And gate then the medium or short air blast valve is opened.

Cantilever slide gate

Abstract: A cantilever slide gate is supported on a gate post and on a line post spaced from the fence post on the side opposite the gate opening by means of a pair of brackets, one secured to each post. Each bracket supports a pair of fixed rollers with their axes horizontal in a transverse vertical plane normal to a longitudinal vertical plane through the post. A longitudinally movable track is supported on the rollers by means of two spaced apart top flanges. The track also has two spaced apart bottom flanges which support the gate by means of two pairs of spaced apart rollers secured to the top of the gate with their axes parallel to the axes of the fixed rollers, these rollers resting on the bottom flanges. One pair of the gate rollers is positioned generally centrally of the gate and the other pair is positioned on the side toward the line post. Means are provided to cause the track and gate to move in unison with the gate movement being twice that of the track movement.

Synchronous counting apparatus

Abstract: Apparatus for and the method of obtaining high-speed synchronous counting at speeds and an accuracy which would normally encounter problems due to delays in steering circuits used with the counting flip-flops. This is accomplished by the use of a synchronous AND gate operating in conjunction with a first section of flip-flops for controlling the remaining section of flip-flops.

An automated method for designing logic circuit diagnostic programs

Abstract: This presentation describes a method for generating functional test programs for Large Scale Integrated Circuits (LSI) and Logic Cards having hundreds of logic gates.J. P. Roth's D-Algorithm, and S. Seshu's Logic Simulation Method have both been used extensively for generating logic circuit test patterns.We have developed a more efficient method which incorporates both of these methods.The new method solves diagnostic problems related to the logical circuits obtained by partitioning logic circuits making up the digital hardware.In this presentation, we describe a test pattern generating method, and an Automatic Diagnostic Program Generator (ADP-3) using this method with a FACOM 230-60 computer.

Circuit for reducing pulse pile-up in pulse detection systems

Abstract: The amplified pulses from a radioactivity detector are coupled to a discriminator and via a 400 nanosecond delay line to the inputs of three linear gates The discriminator is AND gated with a clock pulse and a J-K flip-flop A scale of four and a 1 of 4 decoder and a single shot multivibrator are driven by the AND gate output The single shot output and the decoder outputs are AND gated to control the linear gates In an alternative embodiment, the linear gates and delay lines are replaced with charge and hold, delay and interrogate circuits

Multifrequency signal receiving circuit

Abstract: A plurality of bandpass filters equal in number to the number of frequencies of multifrequency input signals supplied thereto select the input signals. Each of a plurality of signal detectors is connected to a corresponding one of the bandpass filters and provides pulse trains corresponding to the frequencies of the signals selected by the bandpass filters. A plurality of OR gates is provided. Each of the OR gates has a first input connected to the output of a corresponding one of the signal detectors, a second input and an output. An additional OR gate has a plurality of inputs each connected to the output of a corresponding one of the signal detectors and an output for providing an output pulse train. A rectifier circuit has an input connected to the output of the additional OR gate and converts the output pulse train of the additional OR gate into continuous signals. A plurality of AND gates is provided. Each of the AND gates has a first input connected to the output of a corresponding one of the plurality of OR gates, a second input connected to the output of the rectifier circuit and an output connected to the second input of a corresponding one of the plurality of OR gates. The outputs are derived from the outputs of the AND gates.

Sequence "and" gate with resetting means

Abstract: Circuit for sensing two signals and producing an output when the signals are in sequence, with resetting means to inhibit the output after a specific time interval has elapsed between the two signals or whenever an intervening other signal occurs.

Safety apparatus for controlling circuits

Abstract: 1,219,262. Logic circuits. C. R. EDWARDS, and J. R. MADLEY. 19 Jan., 1968 [20 Oct., 1966; 1 March, 1967], Nos. 47070/66 and 9646/67. Headings H3P and H3T. [Also in Divisions G4 and H2] A fail-safe logic circuit comprises a plurality of inputs each having two alternative states, an output B having two alternative states, a switch device connected between the inputs and the output and arranged to provide an output in a predetermined state only when each input is in a predetermined state, and a checking or further circuit 24, 25 connected to all the inputs and to the output and arranged to prevent the output taking up the predetermined state unless each input is in the correct state to result in that output state. In Fig. 1 the switch device is an AND gate formed by a transistor 13 and diodes 1, 2, and has its inputs connected to changeover microswitches which may be limit switches on a machine or on process control valves. When the contacts 4, 8 and 3, 6 are closed the diodes 1, 2 are reverse-biased and the transistor 13 conducts to energize a relay 19, the current through the relay coil being insufficient to light the lamp 21. Should either or both switches be operated to open contacts 4, 8 and/or 3, 6 and close contacts 4, 7 and 3, 5, the transistor should cease to conduct as the relay coil must not be energized. To ensure that the relay is not energized, the closing of the contacts 4, 7 and 3, 5 connects diodes 25, 24 across the relay coil short-circuiting it so that the relay releases and the lamp 21 is lit if the transistor still conducts. The transistor 13, the diodes 1, 2 and resistors 11, 14, 15 may be part of a microcircuit, or the microswitches may be replaced by transistors, Figs. 2 and 3 of the drawings accompanying Provisional Specification 47070/66, (not shown). Fig. 1 of the drawings accompanying the Complete Specification (not shown) illustrates the fail-safe logic and checking circuit included as part of a dairy plant. Diodes are plugged into points of the matrix corresponding to the correct initial state of valves V 1 , V 2 &c. Incorrect setting of the valves thus causes a relay RR 1 &c. to be operated so that a command issued by a relay bi-stable circuit F is not transmitted to the corresponding valve operating line X 2 , X 4 &c. The valve contacts VS 1 &c. operate corresponding reed relays A 1 , B 1 &c. so that contacts AS 1 , BS 1 &c. operate in inverse manner to provide a fail-safe logic operation according to the invention. In Fig. 3 (Comp.) (not shown) forward and back contacts respectively operate the output circuit directly and through a transistor relay circuit and in Fig. 2 (Comp.) (not shown) somewhat similar circuits operate a common output circuit through a combining circuit.

Fault detecting and fault propagating logic gate

Abstract: A logic gate has a fault sensing circuit connected to each of its input terminals and connected to actuate a switching means that open circuits the gate output terminal when there is no current flow either into or out of each gate input terminal. A first embodiment includes a photosensitive type current sensing circuit connected to the input terminal of a NOT gate. When a fault occurs at this terminal, a switching transistor actuates to turn off two drive transistors in a buffer circuit, which open circuits the output terminal. A second embodiment is similar but includes a transistor type current sensing circuit connected to the input terminal of a NOT gate. A third embodiment includes two fault sensing circuits connected to each of two input terminals of a NAND gate. Each fault sensing circuit connects to turn off the two drive transistors in a buffer circuit when a fault occurs at either input terminal. And finally, a fourth embodiment includes a fault sensing circuit connected to each of two input terminals of an AND gate, each circuit connected to deenergize a relay coil which opens a switch in the gate output terminal when a fault occurs at either input terminal.

Improved logic circuit using a current switch to compensate for signal deterioration

Abstract: An improved logic circuit comprising an input semiconductor, an output semiconductor and a current switch connected therebetween to compensate for signal deterioration in the logic circuit. The input semiconductor is biased to remain unsaturated in response to a binary signal swing at an input terminal. In an AND gate, the input semiconductor is a multi-emitter transistor; in an OR gate, the input semiconductor is a plurality of transistors.

Phase-shifting circuits

Abstract: 1,254,223. Active filters; phase lock circuits. INTERNATIONAL BUSINESS MACHINES CORP. 25 June, 1969 [5 July, 1968], No. 31971/69. Heading H3A and H3U. A phase shifter comprising capacitors C1 ... C4 connected to an input 1 via respective input switches S1 ... S4 and to an output 1 11 via respective output switches S5 ... S8 is characterized by the provision of means for varying the relative operating time of corresponding input and output switches to vary the phase shift. A second set of output switches operated at different phases from switches S5 ... S8 may be added to give a different phase output, Fig. 9c (not shown). The circuit may be used in a data transmission system, for locking the phases of the received modulated carrier and the data rate to those of locally generated carrier and clock signals respectively. The carrier lock circuit, Fig. 3, comprises a phase shifter SF2 of the type described fed with the received carrier signal to provide a first input to a phase comparator " LOGIC." The local signal provides a second reference input p and the resulting error output from the comparator is applied to an AND gate together with the output from an oscillator OSC2, to adjust the timing of the output switches of the phase shifter relative to the input switches. The output from the oscillator is fed to a first divider path d3, d4 to operate the input switches, and a second similar divider path is included between the AND gate and the output switches. The dividers may comprise a chain of binary circuits with the necessary outputs taken from different points along the chain. Fig. 6 (not shown). In this Figure, the comparator " LOGIC " is shown to produce further timing pulses which vary the timing of output pulses from divider d5, d6. The data lock circuit, Fig. 9a (not shown), uses a similar control circuit in which a phase shifter (SF4) is fed with data signals and is controlled by an oscillator (OSC) via a divider (d 11 ). A modification, Fig. 9b (not shown), employs the phase shifter of Fig. 9c (not shown), to give phase displaced outputs.

Improvements in or relating to redundancy reduction systems

Abstract: 1,235,007. Television. WESTERN ELECTRIC CO. Inc. 11 Nov., 1969 [13 Nov., 1968], No. 65042/69. Heading H4F. General.-In a redundancy reduction television transmission system for matching the transmitted signal to the limited bandwidth of a channel 403 and/or to enable TDM over the line of a plurality of different video transmissions, the framed video signals are sampled and digitally encoded on to lines 101. A digitized sample or word is fed to comparison circuit 13 and also via gate 14 to a frame memory 21. The word at the same position in the previous frame is read out from the memory 21 and fed via gate 17 to the other input of comparison circuit 13. Each word lasts a period T A , defined by sync. and address generator 11 which also produces pulses # 1 , # 2 and # 3 defining the final, second and last third of T A , and also the coded address A (line and element in that line) of the word on line 101. When the circuit 13 detects a significant difference between the real time and stored words, the real time word is read into the frame memory and a matrix flag memory 22 is energized at a location address corresponding to that of the new word. An entire line of memory 22 is read out during periods # 1 , or # 3 , into group flag register 29 and is there searched for an energized location (i.e. an indication of a new " new word "). Detection of such a location causes the read out of the word from memory 21 into data register 27 for subsequent transmission at the next " transmit order " from transmitter 40. Details.-During # 1 the word in memory 21 at location A from the previous frame is read out to comparison circuit 13 via enabled gate 17. If there is a change, signal on line 131 enables gate 14 to write in new video during # 2 . If there is no change, absence of signal on line 131 enables gate 15 and the word from the memory is re-stored. When there is a change, signal on 131 enables gate 18 such that during # 2 , address A in flag memory 22 (identified by the address signal A at input 228) is energized. During # 2 , a " ready " signal is on line 330 such that if a " transmit " order appears on 401, gate 37 gives a 1 setting bi-stable 31 and enabling gate 32. The word stored in register 27 is thus read through to the transmitter. During # 3 , bistable 31 is cleared and the 1 to 0 transient at the " zero set " input clears register 27. Gate 32 is also closed and bi-stable 33 set. The " ready " signal is removed and gate 34 receives a 1 signal. If input 351 of gate 34 is enabled, bi-stable 35 is set indicating that a new flagged (changed) word has been found during a previous search. Gate 34 gives a " read-restore " order pulse, which sets bi-stable 28 and is fed to the " read-restore " input of memory 21. The " read-restore " order also enables gate 25 and gate 20 via gate 43. The address of the flagged word to be read out of memory 21 at # 3 is F, as generated by 38, 39 and is fed to " address input " of 21 via gate 20. The word at this address is read out by the " read-restore " order, together with the address F, through gate 25 into register 27, provided that during # 2 a " transmit " order was received and acted upon. The " read-restore " order sets bi-stable 28 to enable gate 44. At the next # 1 , the enabled gate 44 gives a signal clearing bistables 33, 28, 35. Bi-stable 28 is now ready to receive the next " read-restore " order and bistable 33 produces the " ready " signal such that register 27 is " ready " to transmit its newly stored data during the next # 2 in response to a " transmit order". The cleared bi-stable 35 gives a #1 signal on 352 which is an order to search for a new flagged word in memory 22. Generator 41 feeds very high-frequency stepping pulses through enabled gate 26. Gate 26 is inhibited during # 1 and # 3 , but not # 2 by " read " order from bi-stable 30 which gives said " read " order when set at the end of a line when element counter 38 gives an " end of line " pulse on 381. The " read " order is fed to the " read " input of memory 22 during # 1 and # 3 . An entire line G in memory 22 is read out into register 29. Number G is fed into memory 22 via gate 24. When the read out is complete " read " order from 42 is fed via delay 36 to clear bi-stable 30 and prepare it for the next end of line pulse from 38. The clearing of 30 removes the inhibit signal from gate 26 such that the " search " " order and the stepping pulses can pass to the register. Each element is read out in turn until an energized flag address is detected, setting bi-stable 35. The stepping pulses also advance counter 38 such that the number of the address F is given. The setting of 35 removes the " search " order such that no further stepping pulses advance the register or counter. The detected " changed " word is read out of memory 21 during the next # 3 provided register 27 has been emptied. Transmitter 40 may be connected to a plurality of systems like that shown, and may transmit then as a TDM basis. The rate of the " transmit " orders is 1/10 that of the word frequency.

Dollar bill or like paper currency collector

Abstract: 1,224,563. Paper currency collector. ROWE INTERNATIONAL Inc. 24 April, 1968 [26 April, 1967], No. 19409/68. Heading G4X. A dollar note or like paper currency collector comprises a passage 56, pairs of rollers 10, 12; 18, 20; 24, 26; and 42, 44a extending into the passage for propelling the note from the passage entrance to the exit where it is collected, means for serially performing a plurality of tests on the currency while it traverses the passageway, and means immediately operable on failing any one of the tests for reversing the roller drive and returning the currency to the entrance of the passage 56. In passage 56 a magnetic reading head M tests the magnetism and line spacing of the note, a lamp L 2 and photo-cell P 2 test line spacing optically, lamps L 1 , L 3 , L 4 , L 5 , L 6 and respective photo-cells P 1 , P 3 , P 4 , P 5 , P 6 monitor the passage of the note, these all being connected to logic circuitry which reverses the feed of the rollers to immediately return the note via the entrance if it fails either test or if the patron attempts to withdraw it illegally by string or paper attached thereto. The note is inserted portrait uppermost and light from lamp L 1 is cut off from photo-cell P 1 sending a pulse through amplifier 101, and OR gate 114 to one input of AND gate 134, the other input of which is enabled from a previous operation. Gate 134 activates a synchronous motor or low slip induction motor 38 driving forward the rollers 10, 18, 24 and 42. AND gate 116 is also enabled, a pulse sent through OR gate 138 to winding 35 of solenoid 36 thus drawing roller 22 away from head M. The note is drawn by the rollers till the leading edge masks lamp L 3 , amplifier 103 emits a pulse through OR gate 114 to keep gate 134 enabled when the rear edge passes L 1 . Gate 116 is inhibited and the roller 22 is moved to press the note against head M. The roller 20 is magnetic and magnetizes lines of magnetic ink on the note, which magnetism is detected by head M. If the number and magnetic intensity of the lines is sufficient a signal is passed, through wide band A.C. amplifier 108 and tuned amplifier 110, of higher value than a voltage in hysteresis circuit 158 and trigger 160 inhibits AND gate 174. If the intensity is not sufficient, trigger 160 sends no signal, AND gate 174 sends a signal to OR gate 178 and reverse drive is connected by bi-stable 128. At the same time the roller 22 is retracted. If the magnetism is too high, detectors 146, 148 cause trigger 154 to reject the note. However, the inclusion of resistor 142 ensures the detectors respond to RMS values rather than peak. values, so a small piece of highly magnetic material on the note will not cause rejection. If the note passes the magnetic test and has reached lamp L 4 , gate 180 is inhibited, thus allowing the photo-cell P 2 to pass signals, to detectors 166, 168, which measure the amount of light passing through the note and hence the number of lines thereon. If the note is sufficient gate 176 is inhibited, if not photo-cell P 5 causes gate 176 to reject the note as before through OR gate 178. If the note passes these tests it is drawn on by rollers 42, 44 and the leading note edge rotates spring-biased lever 48 anticlockwise which blocks photo-cell P 6 thus sending a continuing drive pulse to gate 134. If the patron has attached a long paper strip to the note in order to illegally pull it back, a pulse from photo-cell P 1 is still present, AND gate 117 emits a pulse which returns the note as before. If the patron attempts to withdraw the note by string, one of photo-cells P 3 , P 4 , P 5 (depending on note position) sends a pulse to OR gate 178, thus rejecting the note. If the note goes past lever 48 and withdrawal is attempted, the lever rotates clockwise and he will only tear off part of the note. When the rear note edge has passed photo-cell 106 a bill collected signal is sent from gate 124 and the motor is stopped. The amplifier 110 has Q values between 20 and 160 and that of amplifier 102 between 3 and 28.

Circuit for improving data in pulse detection systems

Abstract: The amplified pulses from a radioactivity detector are coupled through a delay line to a linear gate. The amplified pulses from the detector are also connected to a discriminator. The output of the discriminator is AND gated in a logical gate with a clock pulse which is synchronized with a high energy neutron source. The AND gate triggers a single shot multivibrator which in turn triggers the linear gate. The delay line allows for the time required for the detector pulse to rise to the discriminator threshold and for the propagation delay in the logic circuitry. The linear gate opens before the arrival of the detector pulse and closes after it passes through. In this embodiment, any detector pulse having the necessary discriminator level occuring within the clock pulse interval passes through the linear gate as a full width pulse. In an alternative embodiment, a J-K flip-flop circuit is triggered by the trailing edge of the single shot multivibrator to disable the AND gate, thus causing the linear gate to pass only the first detected pulse having the necessary discriminator level.

Improvements in or relating to logic circuit arrangements

Abstract: 1,256,068 Transistor pulse circuits PLESSEY CO Ltd 24 Jan, 1969 [7 Dec, 1967], No 55798/67 Heading H3T [Also in Divisions G1 and H1] In a logic circuit, a capacitance C O , Fig 3, which is inherent in a device such as a MOST M1 receiving an information input V I , accepts and stores the information under the control of a clock pulse #, applied through a capacitor C and supplying the power for the logic circuit The circuit acts as an inverter; a negative input ("1") turns on the MOST M1, and the capacitor C O maintains O V output; a zero voltage input ("0") turns M1 off and the output V O is a negative pulse derived from the negative clock pulse by the potential divider C, Co A delay element (Fig 4, not shown) uses two of the Fig 3 inverters in cascade, and controlled from separate clock pulse sources # 1 and # 2 Two (or more) of these elements form a delay line (Fig 6, not shown), in which the clock pulses must overlap if a two phase source is used, but not if three or more phases are used "Write-in" to an intermediate stage of such a two-phase delay line is effected (Fig 9, not shown) by a series pair of MOST's (M16, M17) receiving respectively a negative control pulse and the information input, so that when both are negative, the next MOST stage (M13) is turned on; at the same time the control pulse turns on a MOST (M15) in parallel with a preceding stage MOST (M11) to inhibit same In an alternative "write-in" arrangement, the pair (M16, M17) is replaced by a gating MOST (M19) with its source-drain path in the input line to the gate of one stage (M14) of the delay line, the gating MOST (19) having the control input at its gate Shift/storage circuits use bi-stable pairs of the Fig 3 inverters (Figs 11, 12, 13, not shown) A plurality of cascaded inverters (Fig 15, not shown) operates from a single phase clock pulse source, but the number of stages is limited due to the progressive reduction of pulse amplitude and steepness of pulse edges through the stages A counter/register (Fig 18, not shown), said to be known, is constructed with the Fig 3 inverters and consists of: three MOST's (M33, M34, M35, Fig 19, not shown) with a common drain capacitor (C19) receiving # 1 clock pulese, forming a NOR gate; an AND gate having MOST's (M37, M38) fed from the NOR gate and from an input Do and controlled over capacitors (C20, C21) from the two phases of the clock source; and a bi-stable delay stage (as in Fig 13, not shown) comprising three MOST's (M39, M40, M42) and an inhibit MOST (41) An integrated circuit construction is disclosed Bipolar transistors may be used Instead of a MOST, an opto-electronic diode (Do, Fig 24, not shown) may be used as the device whose inherent capacitance stores the information Here, the clock pulse, or "address", is applied through a capacitor (C26) as before to charge the diode Do capacitance If the information input, in the form of light falling on the diode, causes the capacitance to discharge, then a predetermined voltage signal applied subsequently to C26 fails to turn on a MOST (M52); but if the diode (Do) has held its charge, the predetermined voltage will be sufficient to turn on the MOST (M52)

Pulse frequency divider

Abstract: A frequency divider has an AND gate having an output connected in common to the reset inputs of a chain circuit of bistable flip flops. The frequency divider drives a presettable number of pulses of an input pulse train from the flip flops via a selector switch connected to their outputs. The outputs of the flip flops are connected to the inputs of the AND gate via preselectable circuit connections for setting the denominator of the number of pulses.

Improvements in or relating to limiter-discriminator and gate circuits

Abstract: 1,243,391. Frequency discriminators; limiters. SPRAGUE ELECTRIC CO. 30 July 1968 [31 July, 1967], No. 36269/68. Headings H3A and H3T. A frequency discriminator comprises: a limiter 10 producing a reference signal on line 80; an LC circuit 12 producing, from the reference signal, a signal at 24 which is in quadrature with the reference signal at the carrier frequency; differential gates 94, 95 controlled by the quadrature signal; a differential gate 96 controlled by the reference signal; and an integrator 93 coupled to the gates 94, 95 to produce an output proportional to the phase difference between the two signals. The phase difference between the two signals determines the proportion of the switching cycle for which current is fed from constant current source 92 to load 119. Push-pull output may be provided, Fig. 5 (not shown). The limiter 10 comprises three stages 32, 34, 36, intercoupled by emitter followers 33, 35 with a negative feedback path via resistor 40. Bias potentials are derived from diode chain 11.

A digital measuring instrument including an intergrating analogue-to-digital converter with a clock oscillator and apparatus for phase-locking the operating frequency of the oscillator to a reference frequency

Abstract: 1,245,578. Automatic phase control. SOLARTRON ELECTRONIC GROUP Ltd. 10 Sept., 1968 [11 Sept., 1967], No. 41428/67. Heading H3A. An analogue/digital converter in which a clock oscillator phase locked to a reference frequency comprises a discriminator responsive to a reference signal to sense periodic deviations of the oscillator frequency from a predetermined multiple of the reference frequency, and means responsive to such sensing to reduce the deviation in a stepwise manner. A mains frequency reference input is squared in unit 11 and divided by two in bi-stable 12 to produce on line 12a a 25 c/s. signal, the positive transitions of which set bi-stable 13 and open gate 14 to pass 1 Mc/s. pulses from oscillator 10 to counter 15. After a a count of 19,999 counter 15 produces an output which resets bi-stable 13. If the oscillator frequency is too high, bi-stable 13 is reset before the signal on line 12a makes its next negative transition, to produce a "1" on line 13b and a "0" on line 13a. When the negative transition occurs, this triggers bi-stable 17 to the state in which Q = 0 and Q = 1. During the 10 ms. preceding a positive transition on line 12a, gate 29 is opened to produce a "1" at its output. During the time that 12a and 13b are both "1", gate 32 passes pulses from oscillation 10 to counters 33, 30 and if more than two pulses are passed, 30 switches to "1". The outputs from units 29, 18, 30 are fed to AND gate 20 and coincident "1's" on all three inputs produce a positive signal on line 21. This is fed to diode pump 23 and integrator 24 to produce a signal to slow down the oscillator. If the oscillator frequency is too low, bistable 13 is not reset until after the signal on line 12a makes its next negative transition. When this transition occurs there is thus still a "1" on 13a and a "0" on 13b, and bi-stable 17 is triggered, to the state in which Q = 1 and Q = 0. In this case, during the time that a "1" exists at the outputs of 29, 30 the gate 19 is opened and a negative signal is produced on line 22. This is fed to diode pump 26 and integrator 24 to produce a signal to speed up the oscillator. Units 30 ... 33 provide a dead zone, no correction being applied unless 33, 30 count an error of at least plus or minus two cycles. Units 30 ... 33 may be omitted, and 19,20 replaced by two input gates.

Overload protection arrangement

Abstract: 1,254,640. Protective arrangements. BANDSTAHLKOMBINAT SITZ EISENHUTTENSTADT VEB. 3 July, 1969, No. 33634/69. Heading H2K. [Also in Division G1] An overload protective arrangement, e.g. for a motor, comprises a KWL meter 1 having a rotatable disc with a speed of rotation dependent on the power drawn by the load, means 2 to derive pulse signals from the disc of a repetition frequency dependent on the speed of rotation and an overload indicator which responds when the pulse frequency exceeds a predetermined value. The disc has markings which are scanned by a pulse scanner 2 comprising a light source and a light responsive diode. The pulses are amplified at 4 and supplied to a trigger circuit 9 the output of which is applied to an AND gate 13 and to a monostable circuit 10 also connected to the AND gate 13. The circuit 10 assumes its unstable state for a fixed period as, say, a first pulse ceases. Should the next pulse arrive while the circuit 10 is still in its unstable state then the AND gate 13 has signals on both its inputs and provides an output signal to a storage circuit 14, 15 and amplifier 16 and a relay 17, 18. A feedback signal for the trigger circuit 9 may be provided by an AND-gate 6, an amplifier 7 and an OR-gate 8. The storage circuit 14, 15 may be reset by a switch 20.

Apparatus for and method of integration detection

Abstract: A variable frequency clock is slaved to phase encoded data arranged in sequential bit cells. The phase encoded data is then exclusively OR''ed with the output of the clock and applied to a pair of AND gates which are alternately enabled during successive bit cells. A pair of integrators operating in a differential mode and utilizing negative feedback are provided, one for the output of each AND gate, to alternately integrate successive bit cells. Since each integrator must only integrate over every other bit cell, ample squelch time is provided after each integration thereby assuring return to the squelch reference level.

Zero suppression circuits in high speed numeric printing

Abstract: 1323763 Zero suppression MOHAWK DATA SCIENCES CORP 15 Oct 1970 [15 Dec 1969] 49118/70 Heading G4H In a high speed printer, selectively controllable zero suppression circuits 20a-20n are provided, to prevent the printing of unwanted zeros. Data to be printed is fed to store 6 and then to a series of buffer registers 8a-8n each controlling one column of print. The data then passes to zero detectors 9a-9n and comparators 10a-10n. The other input of comparators 10a- 10n is supplied from a counter 13 which is incremented by the output of a magnetic clock pulse generator driven by the print drum 1. The counter is reset by a pulse produced once per revolution by the clock pulse generator. When agreement is obtained between the inputs of comparators 10a-10n the stored data to be printed agrees with the character on the print drum in the print position, and the print hammers are actuated via AND 16a-16n and drivers 3a-3n. AND gates 16a-16n are inhibited on alternate clock pulses via inverter 19 to permit the paper to advance. The AND gates 16a-16n may also be inhibited on lines 28a-28n by zero suppression circuits 20a-20n. Zero suppression.-The output of zero decoders 9a-9n which detect the presence of print zero data in buffer register 8a-8n, is fed to AND gates 20a-20n. If zero suppression is not required in particular columns, appropriate ones of contacts 25a-25n are closed, inhibiting the appropriate AND gates 21a-21n via inverters 26a-26n. If contact 25a is open and a zero is indicated on line 11a an inhibit signal is applied to AND gate 16a on line 28a, and an enabling pulse is supplied via OR gate 23 to AND gate 21b. Thus for zero suppression to be produced by circuit 20b either a zero must be present on line 11a or contact 25a must be closed inhibiting the operation of the preceding zero suppression circuit 20a. Successive zero suppression circuits 20c-20n operate in a similar manner. (For Figures see next page.)

Pulse generating circuits

Abstract: 1,241,016 Delay circuits BRITISH BROADCASTING CORP 27 May, 1969 [7 May, 1968], No 21497/68 Headings G4A and G4C An output pulse is produced after a pulse has been recirculated through a delay device a predetermined number of times, each recirculation being registered on a counter A first pulse from 16 starts a pulse circulating through the loop 12, 13, 10a, 10b, 11, each circulation being registered in a counter 15 which opens AND gate 20a when it reaches capacity so that a pulse from 10b produces an output A At the same time AND gate 11 closes to stop the circulation, and counter 15 is cleared from 20a An intermediate output can be taken from 10a and an intermediate stage of the counter by gate 20b In a modification recirculation round a loop 10, 13 is started by a pulse at 19 and continues indefinitely the counter enabling outputs A, B at full and intermediate capacity

Fail safe electronic instrumentation for - varying chemical and physical parameters

Abstract: A series parallel arrangement of AND gates, square wave gating generators and input/output devices provides multiple paths for any one parameter. When of the "n" possible transmission chains for the parameter "m" remain blicked at any one time, the transmission is interrupted. Before every AND gate in each chain is a threshold gate circuit and all "n" chains are linked to a common point before the threshold circuits in the corresponding chains so that the these circuits receive a unitary input signal.