Showing papers on "Arithmetic logic unit published in 1976"

Digital computer structure providing arithmetic and boolean logic operations, the latter controlling the former

Abstract: A digital computer of relatively simple and efficient structural organization which is capable not only of conventional arithmetic operations according to a program but also of (i) performing chained Boolean logic processing on any selected bit of any of various selected words held in memory, (ii) using the logic processing result by storing it at any selected bit location in any of various selected words held in memory, and/or (iii) causing different, predetermined instructions within a program to have their execution dependent upon the results of previously performed single bit logic processing. The logic processing is carried out in response to specially coded instruction words which may be randomly interspersed between conventional arithmetic instruction steps within an overall program. Existing registers and apparatus components necessary for conventional arithmetic operations are utilized in large measure to carry out the routing of signals to and from the logic processor, and very little added hardware is required to create the logic processing, storing, and dependent conditioning.

Oversized data detection hardware for data processors which store data at variable length destinations

Abstract: Size exception detection hardware for use with a digital data processor arithmetic unit for providing high-speed detection of lost data which results from storing an arithmetic result in a destination which is smaller than one or both of the source operands. In response to data processing machine instructions, the arithmetic unit performs arithmetic operations on variable length operands and sends the arithmetic results to variable length destinations. The operand and destination lengths are specified by length fields in the machine instruction. The destination length is specified independently of at least one of the operand lengths and hence may be less than such operand length. The size exception detection hardware looks at both the output field of the arithmetic unit and the destination length field in the machine instruction and generates a size exception program interrupt signal when the part of the arithmetic unit output field located outside of the destination length contains significant data. The size exception interrupt is generated during the same machine control cycle during which the arithmetic unit performs the arithmetic operation which gives rise to the size exception.

Microprogrammed processor system having external memory

Abstract: A data processing system including a central processing unit and external memory. The central processing unit has an arithmetic logic unit having first and second inputs and an output for outputting data. The arithmetic logic unit inputs are selectively connected to the outputs of a plurality of addressable registers which registers have inputs connectable to the arithmetic logic unit output for receiving and storing data therefrom. Additionally, the central processing unit has a read only memory capable of storing a plurality of addressable control instructions and having a plurality of outputs for supplying control signals in dependence upon the addressed control instructions and means capable of addressing control instructions stored in the read only memory in a predetermined sequence, or addressing a selected one of said word locations in dependence upon the data outputted from the arithmetic logic unit. The central processing unit, additionally, has a means for carrying signals adapted to be applied to the external memory for addressing the external memory and for storing data therein.

Electronic calculator or microprocessor having a multi-input arithmetic unit

Abstract: An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is implemented with a semiconductor chip having a arithmetic unit and memory system. The arithmetic unit and memory system include a plurality of operational registers and an arithmetic unit having two inputs and an output. A plurality of operational registers selector gates interconnect the operational registers and arithmetic unit for connecting any selected two of the plurality of operational registers to the inputs of the arithmetic unit. The plurality of operation register selector gates preferably comprise individual MOS transfer gates.

N-channel field effect transistor integrated circuit microprocessor requiring only one external power supply

Abstract: An N-channel field effect transistor microprocessor includes an arithmetic logic unit, a plurality of working registers and address generating circuitry coupled to an internal bus. Control circuitry is coupled to the arithmetic logic unit, the working registers, and the address generating circuitry for producing control signals for controlling operation of the arithmetic logic unit, the working registers, and the address generating circuitry. The microprocessor requires only a single external power supply, and includes means connected to the external power supply for providing electrical energy to the working registers, the arithmetic logic unit, the control circuitry, and the address generating circuitry in order to effect operation thereof.

Electronic calculator or microprocessor with mask logic effective during data exchange operation

Abstract: An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is implemented with a semiconductor chip having an arithmetic unit, an address register responsive to the input, an instruction word memory for storing a number of instruction words and addressable by the address register, and instruction word decoder logic for decoding the instruction words and for controlling the arithmetic unit in response thereto. The system further preferably includes a plurality of operational registers for storing numeric data received from the input or outputted by the arithmetic unit and a plurality of operational register selector gates coupling the operational registers with the arithmetic unit or with each other. The instruction word decoder logic includes mask logic for generating mask signals to the plurality of operational register selector gates. Thus the instruction word decoder logic decodes instructions for operating selected ones of the plurality of operational registers to effect arithmetic operations by coupling selected operational registers to the arithmetic unit or data exchange operations by coupling selected operational registers together. The mask logic also controls the selected operational registers for determining what portions of the words of numeric data stored in the operational registers are to be operated on arithmetically by the arithmetic unit or to be exchanged during data exchange operations.

Central processing unit for numbers represented in the system of residual classes

Abstract: According to the invention, the central processing unit for numbers represented in a system of residual classes comprises registers of first and second operands which are connected to generators, a multiplier, a divider, a shift unit, a modular arithmetic unit, and an analysis system. The analysis system is connected to sign registers, a result sign register, an overflow attribute register, and a result register. The result register is connected to the multiplier, the divider, the shift unit and the modular arithmetic unit. The invention makes it possible to develop a fundamentally novel family of computers operating with numbers in the system of residual classes.

Electronic calculator or microprocessor having a hexadecimal/binary coded decimal arithmetic unit

Abstract: An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is implemented with a semiconductor chip having a hexadecimal/binary coded decimal format arithmetic unit for performing arithmetic operations on numeric data inputted by the keyboard further, the system preferably includes an input, an address register responsive to the input, a instruction word memory for storing a number of instruction words and addressable in response to the address stored in the address register, and instruction word decoder logic for decoding instruction words outputted from the instruction word memory and for controlling the arithmetic unit in response thereto. The arithmetic unit is operable in a first mode for providing an output from the arithmetic unit in binary coded decimal format and in a second mode providing an output from the arithmetic unit in hexadecimal format.

Random number generating unit

Abstract: PURPOSE: In the arithmetic operation of an arithmetic unit which performs the prescribed arithmetic operation repeatedly, the input signal is supplied in asynchronous with the arithmetic operation processing, thereby obtaining a random number generating unit with a simple constitution COPYRIGHT: (C)1978,JPO&Japio

A 16-bit LSI minicomputer

Abstract: A 16-bit LSI minicomputer, using n-channel MOS technology, has been developed. The instruction set contains 126 instructions including floating-point arithmetic and is fully compatible with commercially available minicomputers such as the TOSBAC-40 and the Interdata 70. An execution speed of 2 /spl mu/s is obtained for register to register (RR) instructions. All the central processing unit (CPU) functions are implemented on a single board. An external microprogram ROM and short-single address microinstructions are used to realize high-system performance and reduce the chip area and the package pin numbers. Two LSI chips for the system, a single-chip processor, and a bit-sliced bus controller, are fabricated by a new n-channel MOS technology named the gate oxidation method (GOM) which provides a high-packing density, high speed, and a simplified process.

Computer programming system having greatly reduced storage capacity and high speed

Abstract: A main programming memory device is coupled to an arithmetic logic unit through controllable gating circuitry which permits the majority of control data within the main memory to be sequentially transmitted to the arithmetic logic unit for control of arithmetic data therein. An instruction designation source controls a main memory address device which in turn is coupled to the main programming memory to initiate data readout to the arithmetic logic unit, through the gating circuitry, such instruction designation source also being coupled to a function memory which contains arithmetic logic data unique to particular instructions to be executed. Data source selection bits are associated with arithmetic logic data stored within the main programming memory and control the gating circuitry to cause arithmetic logic data to be transmitted from the main programming memory to the arithmetic logic unit when the source selection bits have a first value, and which cause the unique instruction data within the addressed function memory to be transmitted to the arithmetic logic unit, rather than data from the main programming memory, when the source selection bits have a second value.

Numerical control machine computer - achieves improved speed and accuracy using separate micro-programs for fast and slow operations

Abstract: A numerical control machine computer is designed to be micro-programmable and to provide enhanced accuracy and operating speed with acceptable cost. The interpolation required for numerical conrol machines can also be accomplished without additional hardware. The computer simultaneously processes two different types of programme, one performing the basic numerical control functions and the other carrying out a programme stored internally or externally. The programme containing the interpolation routine is processed faster than that containing such routines as data reading and processing. The commands for the slower programme are held in a store and processed in an arithmetic logic unit under control of a control store. The control store also contains the faster programme commands which is places directly in the processing unit.