Showing papers on "Arithmetic logic unit published in 1977"

Structure for an easily testable single chip calculator/controller

Abstract: A structure for an easily testable single chip calculator/controller comprising an arithmetic logic unit (ALU) and a plurality of active storage elements all interconnected in parallel via an input bus and an output bus. Instructions contained in a read only memory (ROM) are read out into an instruction register. A first means is provided for decoding a portion of the instruction to generate a configuration signal for selectively configuring the logic elements of the ALU. A second means is provided for decoding the remainder of the instruction to generate a register select signal for selectively actuating a chosen storage element. Two test pins are provided, one placed in the input bus and the other placed in the output bus. The test pins are placed in the test mode by the application of a TEST signal to their terminals. Signals from the test pins will be routed to outside diagnostic or testing equipment. All the storage elements may then be read out or written via these two test points by simply decoding an instruction from the instruction register so as to cause the first decoding means to configure the ALU and the second decoding means to access a particular storage unit. The task of testing the chip is simplified since the ALU may act upon any of the storage elements via the parallel input/output bus lines.

Integrated arithmetic unit and digital networks using the unit

Abstract: The invention relates to an arithmetic unit fabricated by large scale integration techniques and to an improved digital network of increased accuracy in which the unit finds application. The integrated circuit comprises an initial summing means, rounding means, full precision multiplication logic and three successive summing means, all elements being successively connected, and all except the first having both internal and external input terminals. The unit is flexible in respect to the length of the operands and their sign notation. The terminals are readily cascaded, permitting interconnection of the unit with like integrated circuit units and with external delay elements. The invention is applicable in a variety of complex operations including digital filtering, correlation, convolution, polynomial evaluation and squaring. In many of these applications, mixed precision and rounding provide increased accuracy in the resulting digital networks.

Digital conference circuit

Abstract: A conference circuit is of a type in which a digital matrix switch (20) under control of a central processing unit (21) responds to a conference request by connecting three or more parties through the digital switch to a digital conference connection processor (28). In a preferred embodiment of the digital processor (28), the voice signal arrives as PCM signals which are on a data line (CIP), and which are successively communicated into various temporary storage means (110, 130, 150 and 160) while undergoing processing in the nature of summarizing signals of all the parties to the requested conference connection and successively subtracting therefrom the signal of each respective party to form the signal sent back to that respective party. This processing is performed under control of a sign bit processor (180) and an arithmetic logic unit (140). In accordance with the invention, sign bit processor (180) effects inversion of alternate sign bits to cancel parasitic echo signals which tend to create oscillating or ringing, thereby creating greater stability in voice transmissions. The resultant signal which is sent back to each party is provided to a gain control register (190). Gain control in 6 db increments is provided by a gain control processor (220) which selectively shifts the word in register (190) according to the size of the requested conference to provide for flexibility of conference sizes.

Organization for an integrated circuit calculator/controller

Abstract: An organization for a single chip calculator/controller which reduces the number of interconnections necessary in an integrated circuit chip. The single chip calculator/controller comprises an arithmetic logic unit (ALU) and a plurality of active storage elements all interconnected in parallel via an input bus and an output bus. Instructions contained in a read only memory (ROM) are read out into an instruction register. A first means is provided for decoding a portion of the instruction to generate a configuration signal for selectively configuring the logic elements of the ALU. A second means is provided for decoding the remainder of the instruction to generate a register select signal for selectively actuating a chosen storage element. The calculator/controller system also includes data clocking and input/output means. The centralization of the logic functions in the ALU allows any instruction to act upon the data contents of any active storage element.

Arithmetic logic apparatus

Abstract: A system includes arithmetic logic units, each including two 2:1 multiplexers, one 8:1 multiplexer, and a three input majority gate. Each 2:1 multiplexer provides a specific one of two data inputs when a select input signal is at a specific one of two binary states. The 8:1 multiplexer provides output signals indicative of specific ones of eight data inputs in accordance with the binary states of three select input signals. Electrical signals indicative of two input variables are coupled, respectively, to the select input of the two 2:1 multiplexers. Two outputs therefrom are coupled to two of three select inputs of the 8:1 multiplexer, and to two inputs of the majority gate. A carry-in signal is coupled to both the third select input of the 8:1 multiplexer, and to the third input of the majority gate. The arithmetic logic unit acts as an adder, subtractor, AND gate, OR circuit, exclusive OR circuit, and NOR circuit. Arithmetic and logical functions on two input binary variables of the form A0, A1. . .An and B0, B1. . .Bn are performed by an arithmetic logic system comprising n+1 arithmetic logic units. The output of the majority gate of one logic unit is coupled to the carry-in signal receiving means for following logic unit. With appropriate control signals, the system acts as an adder by providing a sum function at the respective outputs of the 8:1 multiplexer, and provides a carry-out function at the output of the (n+1)st logic unit majority gate.

Multifunctional arithmetic and logic unit in semiconductor integrated circuit

Abstract: A computing system includes a central processor unit (CPU) in combination with external memory units The CPU includes an arithmetic logic (ALU), an instruction register, a random access memory, and a control system for interconnecting the functional elements of the CPU via sequential use of a common parallel buss, enabling the CPU to be defined on a single chip The ALU is capable of performing eight separate arithmetic and logic functions utilizing common logic gates

Apparatus for performing floating point arithmetic operations using submultiple storage

Abstract: A scientific processing unit includes apparatus for performing floating point multiplication operations with operands in binary coded form. The apparatus is constructed from standard multibit LSI microprocessor chips organized into a number of vertical slices. Each chip includes an arithmetic logic unit (ALU) and a random access memory (RAM). The ALU's are used to generate a predetermined number of submultiples of a mantissa portion of a floating point number which are stored in the chips memories. The submultiples are generated by multiplying the mantissa by predetermined factors which correspond to the values of multiplier digit positions selected during the multiplication operation. The apparatus further includes selection circuits which provide for selection of the least significant bit positions from each of a number of groups of multiplier digits during the multiplication operation. The least significant bit positions selected are used to read out the entire submultiple from the chip memories which thereafter are summed to produce a final product.

Display and keyboard scanning for electronic calculation or the like

Abstract: A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the calculator. The calculator also incudes a program counter, an instruction register, control decoders, jump-condition circuits, a clock generator, a timing generator, digit and FLAG mask decoders, key input logic, a register and FLAG data storage array, a decimal and FLAG arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. Aside from providing basic desk top calculator functions, the read only memory may be programmed so that the system provides metering functions, arithmetic teaching functions, control functions, etc. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal insulator-semiconductor techniques.

Digital differential analyzer

Abstract: A digital differential analyzer comprises an arithmetic unit for performing an integration operation, a control unit for controlling the arithmetic unit, a plurality of temporary storage means in the arithmetic unit for temporarily storing interim results of the arithmetic operation therein to relieve the influence of propagation delay time of the arithmetic unit.

Current mode 4-bit arithmetic logic unit with parity

Abstract: An arithmetic logic unit employing soft-saturating current mode logic gates receives as inputs two 4-bit plus parity bytes and generates a 4-bit plus parity binary output byte in accordance with the particular operational mode prescribed by a binary operation mode control signal. The unit performs sixteen binary arithmetic or sixteen Boolean logic operations on two 4-bit plus parity input fields Ai and Bi. A carry-in input CIN, a carry generate output G, and a carry propogate output P are provided so that the device can be utilized in a full carry look-ahead configuration with a separate carry look-ahead array. A special output F=O is provided for zero detection purposes. In addition to the arithmetic and logic operations, the unit performs parity checking, parity carry, and parity prediction operations on the 4-bit plus parity binary input signals, and accordingly special inputs in the form of a carry-in duplicate CID, parity of the half-sums HS, a parity of the half-parities HP, parity of the carries PC, carry error CE, and parity checking command PCK are provided. A special output E indicates a carry or half-sum parity error. A carry-out signal COUT is also provided. The device can be configured to operate on bytes having fewer than four data bits by means of a pair of configuration select signals P1 and P2.

Current mode 5-bit arithmetic logic unit with parity

Abstract: An arithmetic logic unit employing soft-saturating current mode logic gates receives as inputs two 5-bit bytes and generates a 5-bit binary output byte in accordance with the particular operational mode prescribed by a mode control signal. The unit performs sixteen binary arithmetic or sixteen Boolean logic operations on two 5-bit input fields Ai and Bi. A carry-in input CIN, a carry generate output G, and a carry propogate output P are provided so that the device can be utilized in a full carry look-ahead configuration with a separate carry look-ahead array. A special output F= is provided for zero detection purposes. In addition to the arithmetic or logic operations, the unit generates a parity of the half-sums signal HS, a parity of the half-parities signal HP, a parity of the carries signal PC, and a carry error signal CE. A carry-out signal COUT is also generated.

Current mode binary/BCD arithmetic logic unit with parity

Abstract: An improved binary/binary coded decimal arithmetic logic unit employing soft-saturating current mode logic gates operates on pure binary data or binary coded decimal (BCD) data. The unit performs 16 binary and 2 decimal arithmetic operations and 16 Boolean operations on two 4-bit plus parity input fields. The particular operation is determined by a 5-bit mode control signal. A carry-in input CIN, duplicate carry-in input CIND, parity check PCK input, invert parity input IP, decimal mode signal D, and decimal add input DA are also provided. The device generates a binary output resultant of the operation defined by the mode control signal. In addition to the arithmetic or logic operations, the unit performs parity checking, parity carry, and parity prediction operations on 4-bit plus parity binary and BCD fields.

Arithmetic operation control unit

Abstract: PURPOSE:To give the returning of information to register and to perform arithmetic operation control continuously from the condition immediately before interruption at reapplication of power supply, by making non-volatile the register and the memory unit included in the arithmetic control unit constituted with the semiconductor integrated circuits.

Current mode arithmetic logic circuit with parity prediction and checking

Abstract: A current mode arithmetic logic circuit utilizes a unique combination of a 4-bit and a 5-bit arithmetic logic unit for performing parity prediction and parity checking on an n-bit byte plus parity, in addition to performing 16 binary or 16 Boolean operations on two n-bit plus parity bytes.

A Unified Numeric Representation Arithmetic Unit and Its Language Support

Abstract: This paper describes a combined arithmetic unit and language support system which allows user specifications of the arithmetic. Limited extensions to a high-level language, in connection with a generalized underlying arithmetic unit, allow a single skeletal unified numeric operand type to be refined into a variety of data types. The interpretation of operands by the operators is based on type descriptors, allowing one set of polymorphic arithmetic operators to be defined across all combinations of user-defined operand types. The arithmetic unit is realized in microcode to achieve efficiency.