Showing papers on "Arithmetic logic unit published in 2023"

A Quantum Computing Arithmetic-logic Unit

Abstract: We show that a quantum version of a classical arithmetic-logic unit (ALU) can be implemented on a quantum circuit. It would perform the same functions as a classical ALU, with the possibility of adding quantum functions in conjunction. To create the quantum ALU, we utilized IBM's Python package Qiskit and JupyterLab. We believe that a quantum ALU has the potential to be faster than its classical counterpart and the ability to calculate quantum specific operations. The simple classical functions translated to a quantum circuit show a promising future for the development of a full quantum ALU with unique quantum operations.

8-bit Arithmetic Logic Unit (ALU) using full swing restored M-GDI technique

Abstract: The ALU is an essential operational unit found in every processor, serving as the core component of the CPU. It performs most of the fundamental operations, including logical and arithmetic operations. In this paper, an 8-bit Arithmetic Logic Unit (ALU) is developed using swing restored M-GDI technique and compared with the previous M-GDI technique. The M-GDI technique is area and power efficient technology but the output swing is not obtained fully. To solve this problem a swing restored M-GDI technique applied to previous circuits. The ALU is responsible for performing logic operations (AND, OR, XOR) and arithmetic operations (ADDER, SUBTRACTOR, MAGNITUDE COMPARTOR) using three logic gates: AND, OR, and XOR. The output of the ALU is determined by the input select line and given to the multiplexer. The average power, number of transistors, and delay are the key factors used to evaluate the performance of the ALU, which is implemented in the software CADENCE VIRTUOSO.

Design and Implementation of Arithmetic and Logic Unit (ALU)

Abstract: ALU is the fundamental building block of many processors like Central Processing Unit(CPU), Floating point Unit (FPU's), Graphical Processing Unit(GPU's). ALUs are used in digital computers, and they are a component of logic design whose goal is to create the right algorithms to make the most use of the hardware which was available to us. This research study describes the VLSI design of an ALU and the functionality of this design has been simulated and tested using Xilinx ISE design suite 14.7. which is used to validate the design at gate level and chip level implementation. The proposed ALU is designed using a total of 9 operations which includes Addition, Subtraction, Multiplication, Shifting, Comparison, AND, OR, NOT, and XOR.

Design of efficient reversible floating-point arithmetic unit on field programmable gate array platform and its performance analysis

Abstract: The reversible logic gates are used to improve the power dissipation in modern computer applications. The floating-point numbers with reversible features are added advantage to performing complex algorithms with high-performance computations. This manuscript implements an efficient reversible floating-point arithmetic (RFPA) unit, and its performance metrics are realized in detail. The RFP adder/subtractor (A/S), RFP multiplier, and RFP divider units are designed as a part of the RFP arithmetic unit. The RFPA unit is designed by considering basic reversible gates. The mantissa part of the RFP multiplier is created using a 24x24 Wallace tree multiplier. In contrast, the reciprocal unit of the RFP divider is designed using Newton Raphson’s method. The RFPA unit and its submodules are executed in parallel by utilizing one clock cycle individually. The RFPA unit and its submodules are synthesized separately on the Vivado IDE environment and obtained the implementation results on Artix-7 field programmable gate array (FPGA). The RFPA unit utilizes only 18.44% slice look-up tables (LUTs) by consuming the 0.891 W total power on Artix-7 FPGA. The RFPA unit sub-models are compared with existing approaches with better performance metrics and chip resource utilization improvements.

Propose a Full.Adder based on Bonhemmi project for MTJ Inverter.

Abstract: Abstract In this paper, I proposed new idea for a nano electro.magnetics Full.adder. Simulation and design of inverter and majority.voter is a work on Bonhemmi method and analysis that is based on SST.MTJ method. After this idea, we can design other gated and devices besed on this formula to implement Microprocessor and … . Spintronics devices are based on the up or down spin of the electrons rather than on electrons or holes as in the traditional semiconductor electronics devices. Magnetic processors using spintronics devices in principle are much faster and with the potential features of nonvolatile, lower power consumption and higher integration density compared with transistor-based microprocessor. Full adder is one of the most important basic units of the arithmetic/logic unit for any processors. The design of the full adder determines the speed and chip-density of a processor. In this paper, a novel spintronics full adder is proposed based on novel programmable spintronics logic devices. Only seven magnetic tunnel junction elements are needed for this full adder design.

Design of Low Power Arithmetic logic unit using SHE assisted STT / MTJ

Abstract: : As CMOS technology shrinks to the deep submicron range, increased power dissipation becomes a big issue. Due to its non-volatility, fast speed, great durability, CMOS compatibility, and low power consumption, the Spin transfer torque (STT) switching mechanism based on Magnetic tunnel Junction (MTJ) is widely regarded as one of the most promising spintronic devices for the post-CMOS era. The research presented here proposes a novel Arithmetic Logic Unit (ALU) that makes use of Spin Hall E ff ect (SHE) to aid with STT / MTJ. In this study, we use SHE-assisted STT logic to create a Hybrid Full Adder and three other logics (AND, OR, and XOR). The proposed logics are then used to create an adder circuit, which is used to create an Arithmetic Logic Unit (ALU). A comparison of each of the proposed designs to the DPTL − C 2 MOS − ALU and P-MALU has been performed. The simulation findings show that the proposed designs outperform competing ALU designs, with a 28% reduction in power consumption and a corresponding reduction in latency. For circuit simulation in 45nm technology, the Cadence Virtuoso tool is employed.

50 GHz Operation of RSFQ Arithmetic Logic Unit Designed Using the Advanced Design Flow and the Dual RSFQ/ERSFQ Cell Library

Abstract: Arithmetic Logic Unit (ALU) is an integral part of digital signal processing applications and computing systems. We used ALU, based on Kogge-Stone adder, as a reference circuit to experimentally validate the advanced design flow and the dual RSFQ/ERSFQ standard cell library. Using the advanced design flow, the ALU sub-blocks were optimized across multiple process corners using Monte-Carlo simulations incorporating statistical variations in the process parameters. The correct operation of ALU was verified in the digital HDL simulation using static timing analysis pre-fabrication. We designed the RSFQ 1-bit and 4-bit ALU using the standard cell library approach for MIT-LL 100 µA/µm ² SFQ5ee fab node. For the ERSFQ 1-bit ALU, the bias current overhead for the feeding JTLs was designed to be 100% of the ERSFQ DUT bias current. The RSFQ 1-bit ALU, designed for low frequency functional testing, demonstrated greater than ±15% bias margins. We demonstrated successful operation of the RSFQ 4-bit ALU with greater than ±6% bias margins at 20 GHz, greater than ±5% bias margins at 40 GHz, and greater than ±4% bias margins at 50 GHz clock frequency with BER less than 10 ^-12 . The ERSFQ 1-bit ALU worked up to 30.72 GHz clock frequency with BER less than 10 ^-12 . In addition, we analyzed the model-to-hardware correlation for the INIT sub-block of the ALU. The simulations accounted for critical current density ( J_c ) and sheet resistance ( R_s ) process parameters. We noted the discrepancy in simulated and measured margins and studied that a 15% higher J_c in simulations results in better model-to-hardware correlation for the INIT sub-block.

Design and Implementation of Single Precision Floating-point Arithmetic Logic Unit for RISC Processor on FPGA

Abstract: The main purpose of conducting this research is to design and implement a single precision floating-point arithmetic logic unit (ALU) that considered as a part of the math coprocessor. The main advantage of floating-point representation is that it can support more values than fixed-point and integer representations. Summation, Subtraction, multiplication and division are arithmetic functions in these calculations. In this floating-point unit, input must be provided in IEEE-754 format, which is 32 single precision floating point values. The application of This arithmetic unit is located in the math coprocessor. Commonly referred to as reduced instruction set computation (RISC) processor. In this processor, for a signal processing, a value with high accuracy is required and as it is an iterative process, the calculation should be as fast as possible. A fixed-point and integer central processing unit (CPU) can't meet the requirements. The floating-point representation can calculate very large or very small process quickly and accurately. The system designed, verified and implemented with Verilog hardware description language using Intel Altera software tools.

FPGA-Supported HDL Approach to Implement Reversible Logic Gate-Based ALU

Abstract: This manuscript banks on the design of reversible gates and implementation of an Arithmetic Logic Unit – 16 bit (ALU) utilizing Verilog with Xilinx ISE 14.7, Spartan 6FPGA kit. The same functionality is compared with a basic logic gate- based ALU. Reversible gates can produce a distinct output vector from each input vector, and the opposite is also possible. Circuits with irreversible gates suffer from data erosion. Power loss results from a circuit’ s loss of data. In conclusion, gates with reversible logic are preferable over irreversible counterparts. A library of reversible gates, comprising of AND, OR, NAND, NOR, and XOR, using Verification Logic Hardware Description Language (HDL) is developed, which in turn contributes to the designing of arithmetic and combinational logic like full adder, decoder (2: 4), decoder (3: S), multiplier, full subtractor, and comparator.

4-trit CNFET-based Arithmetic Logic Unit

Abstract: With the increase in advancement in chip technology, there is a great need for high-speed Arithmetic Logic Units (ALUs). These should also consume low power. One such technology which is coming into trend is Carbon Nanotube Field Effect Transistor (CNFET). CNFET is becoming popular because of its high speed and low power consumption properties. Ternary logics are now being preferred over binary logics because of several reasons such as high computational power for advanced technologies. The ternary logic uses three symbols, whereas binary logic uses only two symbols thereby it has higher processing capability. Some other advantage of CNFET based circuits is that only with fewer modifications in the existing CMOS-based designs, ternary logic design can easily be created. Simulation results in this work prove the fact that it has low power consumption and reduced delays, which is a milestone and will be useful for several applications apart from ALUs in future.

Design of 7:2 Approximate Compressor Using Reversible Majority Logic Gate

Abstract: Digital signal processing and image processing methods will take precedence over traditional arithmetic operations in the next generation of digital devices. These arithmetic unit's operations will generate a significant amount of garbage signals as a result of this problem, necessitating the deployment of a large number of memory logic components. As a result, the VLSI system architecture will require additional space, latency, and power to perform these arithmetic operations. The approximation computing paradigm, a new revolution in nanoscale computing, is focused with fault tolerance in the computing process in order to improve performance and reduce power consumption in arithmetic operations (Liu et al. in IEEE Trans Emerg Top Comput, 1–1, 2016 [1]). It is possible to apply majority logic (ML) to a wide range of emerging nanotechnologies that have compact building blocks. Additionally, these majority logic gates are even more comfortable with logic reduction in size. In this way, the suggested technique for this study employs reversible logic for approximation arithmetic operations, which will require less memory logic and less power consumption than previous approaches. This suggested methodology also produced six major 7:2 compressor approximation methods using a reversible majority gate, and so established all of the criteria for area, delay, and power.

Design of an Accelerated Squarer Architecture Based on Yavadunam Sutra for Machine Learning

Abstract: A novel acceleration strategy of a squarer architecture is proposed for machine learning so as to reduce the hardware complexity and thereby achieve superior performance. Complex mathematical operation can be greatly simplified by adopting Vedic mathematics. Efficient arithmetic operations are required to carry out real-time applications. Multipliers are frequently employed in signal processing. Hence multipliers can be designed using a squarer unit. Squaring Circuit offers a very good performance in terms of speed. Thus squaring module becomes the fundamental operation in any arithmetic unit. The squaring operation is frequently employed in cryptography also. On the whole, squaring operation is widely encountered in multipliers. While designing multipliers, it is essential to reduce the hardware complexity with less power consumption. Vedic mathematics simplifies the design concepts and thus paves the way for high-speed applications. On comparing the various Vedic sutras, Yavadunam sutra is highly efficient from logic utilization and is found to be suitable for high-speed digital applications. Hence, a squaring architecture has been designed using Yavadunam sutra, an ancient sutra of Vedic mathematics without using a multiplier circuit. The proposed acceleration strategy employs only addition operations. The design is simulated and realized using Xilinx Isim Simulator.