Showing papers on "Bit plane published in 1971"

Bipolar analog-to-digital converter with double detection of the sign bit

Abstract: A bipolar sequential analog-to-digital converter is designed to have two sign bit checks. When the first few encoded bits indicate an input signal near zero, the sign bit is rechecked and the result is compared with the first sign bit detection. When the two are the same, the encoder continues to generate the remaining bits of the code. However, when the sign bits do not match, the previously generated bits are corrected before the encoder generates the remaining bits.

Delta modulation system with randomly timed multiplexing capability

Abstract: The principal feature of this multiplexed delta modulation system is its ability to introduce digital data or other lowfrequency information signals into a high-frequency digitized signal stream at random times, without loss of synchronization or undue degradation of the high-frequency signal. When a lowfrequency data bit is to be introduced into a bit stream representing the high-frequency signal, such a bit first is converted into a multibit code word W1 or W2, depending upon whether a 1 or 0 data bit is to be transmitted. The code word W1 or W2 they may be inserted into the transmitted bit stream at any random time, replacing a bit pattern of corresponding length in said stream which otherwise would represent the coincident portion of the high-frequency signal. The code word W1 or W2 is recognized as a data bit representation at the receiver regardless of where it occurs in the bit stream. If a bit pattern identical with W1 or W2, but not representing a low-frequency data bit, should appear by change in the high-frequency digitized signal, such a bit pattern is altered prior to its transmission so that it will not be mistaken for a data bit at the receiver. The delta modulation process automatically is adjusted to compensate for: (1) any difference between the numerical weight of an introduced bit pattern W1 or W2 and the numerical weight of the bit pattern which it replaces, or (2) in the case of a bit pattern fortuitously identical with W1 or W2, the difference between the respective numerical weights of such a bit pattern before and after its alteration.

Data transmission over pulse code modulation channels

Abstract: An arrangement to substitute data bits for and extract these data bits from at least one channel of a PCM-TDM intelligence (voice) communication system. The data bits do not have to be synchronized with the normal PCM bit stream. The normal PCM bit stream employs n bit positions, one bit position being employed for signalling and/or synchronization and (n-1) bit positions being employed for conveying intelligence. Data bits equal to or less than (n-2) are substituted for intelligence in a selected PCM channel. The data bits are grouped at one end of the (n-1) bit positions and a marker bit is inserted into a bit position adjacent the last data bit. The location of the marker bit in the (n-1) bit positions indicates the number and repetition rate of the data bits. The position of the marker bit within the (n-1) bit positions is employed in the receiver to extract the data bits from the PCM bit stream and to return the data bits to their original repetition rate for further utilization.

Conversion of base b number to base r number, where r is a variable

Abstract: A binary number stored in an N stage register is shifted a bit at a time, most significant bit first, into a serial divider. The divider is adjustable in the sense that it may be set to divide by any number R, where R is the radix of the number system into which the binary number is to be converted. The divider produces a quotient bit in response to each bit it receives and produces a multiple bit, binary-coded character to the new base after each N shift pulses. The quotient bits are shifted back into the least significant bit position of the register as they are produced.

Binary-code expander

Abstract: A compressed eight-bit word, including a polarity or sign bit Qs, three range-indicating bits a, b, c and a group of four significant bits X, Y, Z, W, is reconverted into an original 12bit word by introducing (7 - n) zeroes between the sign bit Qs and the significant group, with n representing the numerical value of the three-bit combination a, b, c, inserting a 1 just ahead of bit X unless a b c 0, and adding a 1 (followed only by ''''0''s'''') immediately behind bit W if this bit is in other than the No. 12 position. A logic matrix, forming part of a range decoder, receives the bits a, b, c from an eight-stage input register to control the transfer of significant bits X, U, Z, W to consecutive stages of a 12-bit expansion register, along with an immediately preceding 1 if any of the controlling bits has a finite value. This group of bits is followed in the expansion register by at least one 1 whose position determines the extent to which the significant group with its leading 1 must be shifted away from the sign bit Qs invariably tranferred to the first stage of that register.

Cascade-feedback analog to digital encoder with error correction

Abstract: A coder for converting an input analog signal into a digital output signal containing first, second and other bit signals, includes a first coding circuit activated by the input analog signal to generate the output of the first coding circuit, a second coding circuit activated by the first bit signal to generate the second bit signal judged at a first time point, a feedback coding circuit energized by the output of the second coding circuit to generate the other bit signals; the first, second and other bit signal constituting the digital signal at an output terminal; the second and other bit signals subject to error due to the level of the output of the second coding circuit at the first time point; and a bit level comparison circuit comparing the second bit signal judged at the first time point and at a second time point succeeding the first time point for producing a comparison signal to correct the second and other bit signals, whereby the first bit signal and the corrected second and other bit signals after the second time point are included in the digital signal at the output terminal.

Binary squaring circuit

Abstract: An apparatus and method for squaring digital binary numbers which operates in cycles starting with the most significant bit followed by the less significant bits in sequence. If the bit being operated upon is a ONE, the smaller number formed from the bits having greater significance than this bit are added to the square of this smaller number (previously determined). The significance of each bit in this sum is increased by two and ONE placed as its least significant bit. However if the bit being operated upon is a ZERO; then the significance of each bit of the square of the smaller number formed from the bits having greater significance than this bit is increased by two and ZERO''s placed in the least significant positions.

Key-operated teleprinter

Abstract: Key-operated teleprinter for the transmission of code symbols by the start-stop method, wherein each key triggers a further bit which has a first value and a second value for letters and numerals respectively, the bit combination and further bit being supplied to a reserve store adapted to store same and a master clock for controlling transmission of said bit combinations and associated further bits from the reserve store to the transmitter sotre, also for controlling the output circuit which transmits the bit combination to the transmission of a bit combination to said line if the further bit transmitted together with the bit combination is different from that transmitted with the preceding bit combination and means for producing an operating character for shifting the receiver from letters to numerals or vice versa.