Showing papers on "Bit plane published in 1976"

DC free encoding for data transmission system

Abstract: A method and apparatus provide for the elimination of any net DC component from the transmission of binary data sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states, e.g., 0's are normally transmitted as signal transitions relatively early in respective bit cells, preferably at cell edge, and logical second bit states, e.g., 1's, are normally transmitted as signal transitions relatively late in respective bit cells, preferably at mid-cell, and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed. The onset of a sequence of second bit states following a first bit state that might introduce a DC component into the transmitted signal with normal transmission is detected by producing a first indicating signal, and in response to the first indicating signal and the state of a current bit and the state of the next succeeding bit the transmission of signal transitions is modified to eliminate any DC component. Preferably, the end of a sequence of second bit states that would introduce a DC component is detected by producing a second indicating signal utilized to modify the signal transitions at the end of a troublesome sequence, as by suppressing the transition corresponding to the last second bit state in such a sequence.

Digital bit rate converter

Abstract: DIGITAL BIT RATE CONVERTERby Alvin L. Pachynski, Jr. ABSTRACT OF THE DISCLOSURE In a digital communication system, apparatus for upconverting the bit rate, f1, of a digital data source to permit digital transmission at a bit rate f2, where f2 > f1. Pulse stuffing techniques are used to insert a fixed number of time slots in the digital data signal such that the ratio of information time slots to stuffed time slots remains constant.The upconverted signal, consisting of nonredundant data bits and stuffed time slots, is interleaved with framing bits prior to transmission over a digital facility. The framing bits provide the synchronization information to enable the receiver to identify the added time slots and to selectively remove the information data bits from the transmitted line signal. The desired data bits are then restored to their original f1 bit rate.

Nearly Instantaneous Companding for Nonuniformly Quantized PCM

Abstract: The technique of nearly instantaneous companding (NIC) that we describe processes n -bit μ-law or A-law encoded pulse-code modulation (PCM) to a reduced bit rate A block of N samples (typically N \cong 10 ) is searched for the sample having the largest magnitude, and each sample in the block is then reencoded to a nearly uniform quantization having ( n - 2 ) bits and an overload point at the top of the chord of the maximum sample Since an encoding of this chord must be sent to the receiver along with the uniform reencoding, the resulting bit rate is f_{s}(n -2 + 3/N) bits/s where f s is the sampling rate The algorithm can be viewed as an adaptive PCM algorithm that is compatible with the widely used μ-law and A -law companded PCM Theoretical and empirical evidence is presented which indicates a performance slightly better than ( n - 1 ) bit companded PCM (the bit rate is close to that of ( n - 2 ) bit PCM) A feature which distinguishes NIC from most other bit-rate reduction techniques is a performance that is largely insensitive to the statistics of the input signal

Method of graphic data redundancy reduction in an optical facsimile system

Abstract: A method of graphic data redundancy reduction in an optical facsimile system wherein picture elements are optically represented by a grey coded number having N digits where N is at least 5 comprising evaluating at least the first N-2 bit planes to determine whether these bit planes should be processed in high or low resolution, and arbitrarily processing the remaining at least one bit plane at low resolution.

Data bit compression system

Abstract: A binary data signal compression system which includes means responsive to a first selected group of bits of the binary data signal, which is less than the total number of bits of the binary data signal, for producing a second selected group of bits which is less than the first selected group of bits but which contains information corresponding thereto. The second selected group of bits and the remaining bits of the binary data signal are hereupon combined to provide the desired compressed binary data signal.

Apparatus for reconstructing a binary bit pattern

Abstract: A binary bit pattern is reconstructed from a block of analog signals corresponding to the number of known bit positions of the pattern being reconstructed. The analog signals, which may take the form of light intensity signals, vary in signal level with the binary level represented as well as with a characteristic which causes the signal levels of the analog signals to vary in a known manner as a function of bit position. In reconstructing the bit pattern, an output signal is developed having a value dependent upon that of at least one of the analog signals which has a known bit level reconstruction. This signal is used for providing a variable threshold having a value which varies in dependence upon the outut signal as modified by a modifying factor which varies in the known manner as a function of bit position. Bit decision circuitry includes a comparator for sequentially comparing the analog signals with the variable threshold to provide bit decision indications.

Common control constant shift reframe circuit

Abstract: COMMON CONTROL CONSTANT SHIFT REFRAME CIRCUIT Abstract of the Disclosure The disclosed reframe circuit utilizes common control circuitry to carry out a reframing operation for any, or all, of a plurality of time division multiplexed digital data groups which are out-of-frame. An old data store is used to store a given number (m) of selected data bits, of each digital group, for two frames for framing comparison purposes. A reframe comparator serves to com-pare, for each digital group, the m bit output of the old data store with m data bits that are two frames later in time. A suitability store is used to record, for each group, which of the compared m data bits have had framing pattern violations and which appears as a suitable candi-date for the framing bit. Based on the present set of comparisons and past suitabilities, a shift decoder searches for the framing bit within the current m-bit window until it has either marked all m bits unsuitable or has found the true framing bit within the window. If all m bits are unsuitable, the data bits of an out-of-frame digital group are shifted m bit positions, m new bits are loaded into the old data store, the suitability store is initialized for these new m bits, and the described operation is repeated. When the shift decoder finds a bit that is suitable for a given number of consecutive frames and hence is the true framing bit, the digital group is placed in-frame by shifting the data bits thereof one to m bit positions.

Expandable memory for asynchronous PCM multiplexer

Abstract: Four bit streams arriving simultaneously over respective incoming lines at a transmitting terminal, connected via a PCM link with a remote receiving terminal, constitute recurrent lower-order frames whose bits are to be interleaved in a composite higher-order frame to be sent on to the remote terminal for redistribution over four outgoing lines. The bits of each incoming bit stream are cyclically written in an 8-stage buffer register at their rate of arrival, the contents of the register stages being read out at a higher rate to allow for the interpolation of ancillary bits constituting supervisory signals. Each higher-order frame consists of four subframes in which the message bits from the contributing bit streams are preceded by one or more ancillary bits; the latter include a discriminating bit in each of the last three subframes indicating whether or not a further bit in the fourth subframe is a stuffing bit or a message bit. The insertion of a stuffing bit, i.e. the delay by one time slot of the readout of a message bit from a stage of the buffer register, is controlled by a comparator receiving writing and reading pulses respectively timing the loading of the eighth register stage and the unloading of the fourth register stage; upon a coincidence of these pulses in a first subframe, a presetting section of the comparator enables an execution section thereof to emit a stuffing command in the following three subframes causing the generation of the discriminating bit at the beginning of each of these subframes and the blanking of the time slot immediately following the last discriminating bit.