Showing papers on "Bit plane published in 1983"

Data compression method for graphics images

Abstract: Graphic images are generally considered to be those images comprised of text and/or drawings. Data compression of graphics images is desired whenever a fast image transmission speed is desired in a limited band width channel. It is also used for storage of a large number of images in a limited capacity storage system. A high compression ratio is achieved by thresholding the graphics image to a bilevel black-white image at one bit per pixel and then employing a second data compression on the black-white image. At low resolution, bilevel images have poor quality at edges and a quality improvement is needed. The data compression apparatus and method disclosed separates the graphics image into at least first and second bit planes identifies edge pixels from the first bit plane indicating a black/white change, locates the edge pixels and generates at least a single bit for each edge pixel indicating whether the edge pixel has a maximum intensity value such as black or white or an intermediate gray intensity value. Intermediate values are not allowed except at edge pixels which enhances both quality and compressibility of the resulting graphics image.

Bit compression coding with embedded signaling

Abstract: A bit compression coding circuit incorporates signaling bit insertion. An input signal sample(s) representing, for example, PCM encoded speech or voiceband data, is delivered to a difference circuit (31) where a predicted signal (s e ) is subtracted from it. The predicted signal is an estimate of the input sample derived from a predictor (32). The resultant difference signal is coupled to the input of an adaptive quantizer (34) which provides at its output a bit compressed quantized differential PCM version of the difference signal. A multiplexer (37) receives the output of the quantizer and serves to periodically preempt the least significant bit of the bit compressed PCM signal and substitute a signaling bit therefor. The output of the multiplexer is coupled to the input of an adder (38) wherein it is added to the predicted signal. The result of this addition is coupled to the input of the predictor, which in response thereto serves to generate the next predicted signal for comparison with the next input signal sample. An adaptation control circuit (36) is responsive to the output of the multiplexer and serves to control the speed of adaptation of the adaptive quantizer.

Bit compression multiplexer

Abstract: A bit compression multiplexer (FIG. 2) for a pair of time division multiplexed digital bit streams each one of which includes a plurality of PCM encoded signals deposited in separate and distinct channels of a repetitive frame and signaling bits multiplexed therewith. The PCM encoded signals of successive frames are normally bit compressed (23) into n-bit signals, but periodically the encoded signals of a frame are bit compressed into n-1 bit signals. The bit compressed signals of the pair of bit streams are time division multiplexed (24) with each other, with the multiplexed compressed signals occupying separate and distinct channels of a repetitive frame. The signaling bits are extracted (21) from the pair of digital bit streams and are inserted (24) into predetermined n-1 bit channels of the last-recited repetitive frame. The signaling bits that are placed in a given channel are related to the encoded message signal of that channel.

Digital word-framing technique and system

Abstract: A method is provided for decoding an encoded signal that includes a series of encoded digital data messages. Each message is encoded in such a way that each bit thereof is contained in the ordering of a complementary bit pair. Each encoded message is separated by a plurality of non-complementary bits. Decoding is provided by simultaneously analyzing a plurality of bit pairs of the encoded signal and producing an output when there are identified (i) a string of complementary bit pairs having a length in pairs equal to the number of bits in one of the messages and (ii) a plurality of non-complementary bits in at least one of the positions immediately preceding or immediately following the string.

Coset code generator for computer memory protection

Abstract: An apparatus for protecting computer memory utilizes a parity matrix to generate an n-k check bit signal of an extended linear (n,k,4) code from a k data bit signal. Exclusive-OR gates add the n-k check bit signal to an n-k tag bit signal selected from a predetermined class, to form, when concatenated with the k data bit signal, an element of a code of a certain class. The element comprising the k data bit signal is written in memory. A correction matrix or And gate cooperating with exclusive-OR gates detects an attempt to access the k data bit signal with an n-k key bit signal belonging to the same class as the n-k tag bit signal, but which does not match it.

Unique start bit for data transmissions

Abstract: In a data transmission system, the start bit is arranged so that at least a portion thereof has a different time duration than a data bit so that the data bit and start bit can be easily distinguished.

Graphics display comparator for multiple bit plane graphics controller

Abstract: A graphic control system under the control of a host processor to display, on a display monitor, high resolution color graphic images. The graphic control system employs a plurality of graphic display controllers each accessing, in parallel, a separate bit map storage area or a plane. When a gray-scale or color display is required, respective planes are read out in parallel and converted for serial transmission with respective outputs being supplied in parallel as a code to a look-up table of color or gray-scale codes that in turn are supplied to a digital-to-analog converter that drives the display monitor. In addition, a compare circuit is provided to receive outputs sent from the respective bit plane stores for comparison with preset outputs from the host computer to determine when the display monitor has reached a boundary of a figure being filled with a particular color or pattern.

Serial comparison flag detector

Abstract: A high speed arrangement for detecting the occurrence of a flag character in a stream of serial digital data signals employs a pattern register in which are stored the bits of the referene flag pattern. As each bit of the serial data is received, it is simultaneously compared by a set of comparators with each of the bits in the flag pattern. The first comparator of the set compares the data bit with the first bit of the flag pattern and each successive comparator compares the data bit with the next successive bit in the pattern. The outputs of the comparators are coupled to corresponding stages of a shift register in the same ordered sequence as the comparators. All the stages of the shift register are arranged to be simultaneously clocked by clock signals. Each stage of the shift register is coupled to the next stage by a gate that permits the shift of a logic bit from the preceding stage to the succeeding stage only when the preceding stage was previously set by a signal from a comparator indicating the occurrence of a match between a data bit and a pattern bit and the gate receives a signal from the next comparator in the set indicating the occurrence of a match between the next data bit and the next pattern bit.

Method of processing picture signal to increase average run length and apparatus therefor

Abstract: A prediction error signal and a prediction state signal are generated for each of a plurality of picture elements (or bit planes or gray codes) to be encoded. The picture error signal is based on a plurality of previously encoded picture element data (or bit plane or gray code). The prediction state signal indicates the probability of the prediction error signal being accurate in one of two probability states. The prediction error signals are classified into two groups according to the probability state indicated by the corresponding prediction state signal. The prediction error signals are then reordered according to a predetermined algorithm. Thereafter, the reordered prediction error signals are run length coded based on the occurrences of incorrectly predicted error signals in the reordered list.

Bit compression multiplexing

Abstract: A bit compression multiplexer for a pair of time division multiplexed digital bit streams each one of which includes a plurality of PCM encoded signals deposited in separate and distinct channels and signaling bits multiplexed therewith. The encoded signals are bit compressed (22), and then multiplexed and grouped (25) into clusters. Each of the multiplexed compressed signals occupies a separate and distinct channel of a repetitive frame that includes a plurality of clusters and a corresponding number of additional channels, called delta channels, each one of which is associated with a given cluster and is proximate thereto. The signaling bits are extracted (21) from the pair of digital bit streams, reformatted (24) and then placed in predetermined bit positions of the delta channels. The signaling bits in a given delta channel are associated with the compressed signals of a cluster proximate thereto. The combination of a cluster and its related delta channel comprise a bundle. A framing bit pattern is developed (23) for each bundle and the framing bits are placed into a predetermined bit position of each of the delta channels (24). The framing bit pattern is arranged to detect frame slips which occur either at a transmitting bit compression multiplexer, at a receiving bit compression multiplexer or at other components of the transmission system, for example, at a Digital Access and Cross-connect System (DACS).

Data processing technique for computer color graphic system

Abstract: A frame buffer, divided into three bit planes, is addressed by a single grahic display control chip, whose address signal is altered by an adder to address each bit plane at successive, prescribed time intervals during a single display cycle. A data word of N-bits from each of the first two bit planes is read and latched, then loaded simultaneously with a data word of N-bits from the third bit plane into corresponding shift registers. Thus, the number of memory chips in the frame buffer is minimized and three times the normal data output is achieved during each display cycle.

Expansion circuit for digital signals

Abstract: A PCM signal processor which converts an analog signal into a digital signal to transmit or record the digital signal. When the PCM signal processor receives a PCM signal whose data has been compressed in such a manner that one or more lower bits are cut off from a plurality of bits for forming the PCM signal and indicating the signal level of the analog signal, in accordance with the signal level of the analog signal, one or more bits corresponding to the number of bits having been cut off are added in the processor to the compressed PCM signal at the position following the least significant bit of the compressed PCM signal (9). Correction data indicating about one half the largest one of numerical values that can be expressed by the added bit or bits, is given to the added bit or bits (30, 31; 26).

Quasi-soft decision decoder for convolutional self-orthogonal codes

Abstract: The present invention relates to a quasi-soft decision decoder for convolutional self-orthogonal codes which includes a multistage syndrome register, a bit detection means, parity check means and threshold logic gates. The bit detection means is augmented to render a "quality" bit in conjunction with each detected data bit which indicates the quality of the received signal level for that bit when compared with a predetermined threshold signal level. Memory storage is provided for storing the quality bits in parallel with memory storage for the data bits. Each of the threshold logic gates includes a separate group of active inputs from the syndrome register plus an associated one of the quality bits, each gate being arranged to generate an information correction bit which is dependent on a predetermined threshold level of corresponding input signals. The quality bit, therefore, provides an additional vote in the decision of whether a suspect data bit is erroneous or not.

Picture information storage system

Abstract: PURPOSE:To effectively store picture information, by storing contracted picture data at each bit plane, storing complementary information for recovery through compressed coding, quickly performing retrieval through the use of the contracted data and coding only required CONSTITUTION:A binary picture data inputted via an input/output device 1 is operated to contract to 1/m(m>1) at an operation controller 4, and the contracted picture data given as n-bit/picture element is compressing-coded at each bit plane and stored 2 Picture display is made by taking the data in the device 2 as retrieval objective, the most significant bit plane picture data only is read out for binary display When the objective picture element is retrieved, the picture data at each bit plane and complementary information required for restoration are read out and upon restorating at the operation processor 4, contributing to quickly obtain the desired picture data

Coding device of binary data

Abstract: PURPOSE:To reduce the low frequency components of a record signal by adding a connection bit to the connection part of a block after coding based on an m/n conversion code system and then controlling properly the connection bit to 1 and 0. CONSTITUTION:A binary data train is divided every (m) bits, and this divided m-bit data is converted into the code data of (n) bits whose zero run length does not exceed (k) units. Then a connection bit MB is added to the n-bit code data, and 1 and 0 of the bit MB are controlled in response to the DSV (digital summation value). Thus it is possible to obtain the code data having a small maximum magnetization inverting interval and a small low frequency component from a binary data train.

Method and an apparatus for synchronizing received binary signals

Abstract: In an apparatus for synchronizing received binary signals, the duration of each bit of the received signals to be synchronized is an integral multiple n of the duration of an original bit, and each original bit has a reception quality factor which is stored in time succession, in respect of the individual original bits, in a common quality factor memory. Quality factor differences of successive original bits are formed by means of a differencing means, and the quality factor differences of those original bits which have the same serial number within a reception bit are added by means of adding circuit. The maximum of the summed quality factor differences of n successive original bits is determined by means of a maximum decision circuit. The addresses of the original bits are continuously adapted in such a way that that of the original bit having the maximum summed quality factor difference receives a given, constant and predetermined value. That original bit is then subsequently used as a first original bit of a reception bit, for synchronization.

Demodulation and error detection circuit for a biphase signal

Abstract: In this circuit, each bit of the bit pairs of the biphase signal is compared with a corresponding bit of an adjacent bit pair or with the clock frequency of the NRZ signal (14, 15, 30, 31). From the first bits of the bit pairs, a first NRZ signal is obtained and from the second bits of the bit pairs another NRZ signal is obtained. Error detection can be effected by comparing the NRZ signals.

Digital modulation system

Abstract: PURPOSE:To control the error rate by high S/N by setting margin bits which are inserted at every (2n-1) bit of the digital information signal executed by (n, 2n-1) bit pattern conversion so that DC components of the digital information signal will decrease and the synchronizing pattern will not occur in the bit pattern. CONSTITUTION:A synchronizing signal which consists of two constant (2n-1) bit patterns from an input terminal 8 is added to the output signal of a code converter 2 by an adder 9, and the output signal is supplied to a margin bit adder 3 and a false synchronizing signal detector 6. When there is the same bit pattern with the synchronizing signal in the part which is not the synchronizing signal part of an output sgnal (b) of the adder 9, the false synchronizing signal detector 6 detects the bit pattern to be the false synchronizing signal, and supplies a detection signal (c) to the margin bit adder 3. The margin bit adder 3 addes the margin bit of two bits at every (2n-1) bit of the (2n-1) bit pattern signal (b). The output signal of the margin bit adder 3 is modulated by an NRZI modulator 4, supplied to the head tape system from an output terminal 5, and recorded.

Oscillator having a sixteen bit signal generation utilizing an eight bit processor

Abstract: A programmable signal generator which utilizes an eight bit microprocessor to generate a sixteen bit signal. Information is passed from an eight bit processor having a sixteen bit address register into one or more latches to produce a sixteen bit digital signal. The generator may be utilized in a time delay spectrometer to produce digital signals in quadrature form which are analyzed by the system microprocessor.