Showing papers on "Blackfin published in 2005"

MINEHOUND production development

Abstract: This paper describes the further engineering development and performance of the MINEHOUND affordable humanitarian mine detector, sponsored by the UK Department for International Development and developed by ERA Technology. Using a radically different patented approach from conventional ground penetrating radar (GPR) designs, in terms of the man machine interface, MINEHOUND offers simplicity of use and affordability, both key factors in humanitarian demining operations. Trials were carried out during the period 2002-2004 and have been reported at SPIE 2002 and SPIE 2004. MINEHOUND has the capability of detecting completely non-metallic mines and offers an affordable solution to hand held mine detection. The GPR is a time-domain radar transmitting 1ns duration impulses at a repetition frequency of 1MHz. The GPR transmitter- receiver and associated control and signal processing is mounted on a compact purpose designed printed circuit board 220mm by 100mm. A dedicated state of the art “Blackfin” DSP processor is used to provide all control and signal processing functions. Trials of batches of MINEHOUND are planned for 2005 in the Cambodia and Angola as well as the Balkans.

Experiences with the Blackfin architecture for embedded systems education

Abstract: In the course of a major curriculum change at California Polytechnic State University, the embedded processing course was redesigned. During this process, the course had the opportunity to purchase new hardware. Analog Device's Black-fin processor was chosen based mostly on cost, but also on performance, development environment, and documentation.We first present our goals in the class. We then give an overview of the Blackfin architecture and how the Blackfin fits in with many of our goals. We then present the implementation of an expansion board developed to interface with Blackfin's EZ-KIT Lite board.We present our experiences with this setup in the hopes that others who might be thinking of a similar curricular change can learn from our successes and failures. We outline the strengths and weaknesses of the Blackfin architecture as an educational platform, followed by a discussion of our experiences and a presentation of the support materials we developed to accompany the course, including lecture material and laboratories. Finally, we discuss our future directions for our uses with the board.

Developing Energy-Aware Strategies for the Blackfin Processor

Abstract: : Energy usage is becoming an increasingly important design constraint for all computer systems. This issue is particularly critical in battery powered, embedded designs. Although many embedded processors have developed sophisticated power management schemes, few have produced an accurate, easy-to-use energy estimation framework. In this presentation we will describe the development of an instruction-level energy modeling framework for the Analog Devices Blackfin family of processors. Using this model, we are able to accurately estimate the energy consumed when running this code. While our main goal is to demonstrate that we can perform accurate energy estimation, we also plan to develop a framework that is fully integrated with compilation in order to produce more energy-efficient binaries. In this abstract we briefly describe our methodology and show data that illustrate some of the difficulties encountered when attempting to statically model energy.

Multilevel optimization of speech coding algorithms for modern DSP architectures

Abstract: Real-time implementation of speech coding algorithm requires the DSP code to be highly optimized and the underlying hardware to be fast. This paper presents the results obtained from multi-level optimization of ITU-T G.729A low complexity speech codec on an embedded DSP platform. The implementation platform used in this work is based on analog devices Blackfin BF533 fixed-point media processor. Several high-level and low-level optimization techniques have been concurrently employed in this work to improve the run-time performance of the codec. Improvement in performance has been evaluated through the reduction in MIPS count for each optimization step. Results show that over twenty full-duplex channels of G.729A can be supported on this DSP platform in real-time.

Implementation of dynamic voltage and frequency scaling on Blackfin processors

Abstract: In this paper, we develop method of scaling voltage and frequency dynamically on Blackfin processors This technique is effective for designing low power real-time embedded systems The objective is to avoid processor being idle in high operating frequency and voltage Instead, processor can save power by running task in lower frequency and voltage and completing it just before the real-time deadline Our method closely monitors the task execution and successfully responds to any change in task computational demand by applying new frequency and voltage The experimental result shows that significant power reduction is achieved Performance level is not degraded since our method always guarantees that execution time is less than real-time deadline Our method can also be implemented in many embedded processors with voltage-frequency scaling feature

Introduction and analysis of Typical Schemes for Embedded Video Surveillance Server System

Abstract: This paper firstly analyzes the present status of the digitalized and Network based video surveillance systems and discusses the key technologies of embedded video surveillance server system. Then two categories of scheme for video surveillance server system, which are based on software MPEG4 encoding on DSP platform and hardware MPEG4 encoding on ASIC platform respectively, are introduced. Several typical systems in each category are presented in detail and the features of them are compared.

Using Cache Memory on Blackfin® Processors

Abstract: Copyright 2005-2009, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of customers’ products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are property of their respective holders. Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices Engineer-to-Engineer Notes. Introduction

A customizable system for real-time image processing using the Blackfin DSProcessor and the MicroC/OS-II real-time kernel

Abstract: This paper presents a development platform for real-time image processing based on the ADSP-BF533 Blackfin processor and the MicroC/OS-II real-time operating system (RTOS). MicroC/OS-II is a completely portable, ROMable, pre-emptive, real-time kernel. The Blackfin Digital Signal Processors (DSPs), incorporating the Analog Devices/Intel Micro Signal Architecture (MSA), are a broad family of 16-bit fixed-point products with a dual Multiply Accumulate (MAC) core. In addition, they have a rich instruction set with variable instruction length and both DSP and MCU functionality thus making them ideal for media based applications. Using the MicroC/OS-II for task scheduling and management, the proposed system can capture and process raw RGB data from any standard 8-bit greyscale image sensor in soft real-time and then display the processed result using a simple PC graphical user interface (GUI). Additionally, the GUI allows configuration of the image capture rate and the system and core DSP clock rates thereby allowing connectivity to a selection of image sensors and memory devices. The GUI also allows selection from a set of image processing algorithms based in the embedded operating system.

Real-time multi-spectral image acquisition and processing on the ADSP-BF533 Blackfin® DSP

Abstract: This paper investigates the ADSP-BF533 Blackfin® processor and its ability to support a real-time multi-spectral imaging system. The Blackfin® Digital Signal Processors (DSPs), incorporating the Analog Devices/Intel Micro Signal Architecture (MSA), are a broad family of 16-bit fixed-point products with a dual Multiply Accumulate (MAC) core. Using the VisualDSP++ software development suite, the ADSP-BF533's ability to host a real-time operating system (RTOS) is investigated, along with its ability to process multi-spectral data sets.

Optimizing the FBI Fingerprint Compression Algorithm for BLACKFIN Processor

Abstract: This paper presents an effective method to convert the conventional floating-point algorithm of the FBI Fingerprint Compression into a fixed-point algorithm suitable for digital signal processors. Wavelet transform, the most computationally expensive component of the technique, is optimized to reduce the computational burden significantly. The conversion and optimization are tailored to fit the advanced structure of the Blackfin processor. The novel algorithm also retains an acceptable quality of the reconstructed image.

The single event effects performance of low power embedded fixed point digital signal processors and microprocessor

Abstract: In this paper, the approach followed to characterize the single event upset susceptibility of the analog devices Blackfin BF533 and Texas Instruments TMS320VC5510 embedded digital signal processors; and the Freescale Semiconductor Coldfire M5249C3 embedded microprocessor using high energy protons, is presented. Single event latchup and total dose effects are also discussed