Showing papers on "Bus network published in 1975"

Bad data analysis for power system state estimation

Abstract: The state estimation problem in electric power systems consists of four basic operations: hypothesize structure; estimate; detect; identify. This paper addresses the last two problems with respect to the bad data and structural error problem. The paper interrelates various detection and identification methods (sum of squared residuals, weighted and normalized residuals, nonquadratic criteria) and presents new results on bad data analysis (probability of detection, effect of bad data). The theoretical results are illustrated by means of a 25 bus network.

Data processing system providing split bus cycle operation

Abstract: In a data processing system which includes a common bus to which a plurality of units are connected for the transfer of information, information may be transferred by the highest priority requesting unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a split bus cycle operation in which the master unit requesting information from the slave unit during a first bus transfer cycle may receive such information from the slave unit during a later slave generated bus transfer cycle. Means are provided for enabling any other units to communicate over the common bus during the time between the first cycle and such later cycle during which the slave unit responds, thereby enabling at least two pairs of units to communicate with each other respectively in an interleaved manner.

Data processing system having distributed priority network

Abstract: A common electrical bus is provided for coupling a plurality of units in a data processing system for transfer of information therebetween. The units are coupled in a priority arrangement which is distributed in each of the units thereby making a bus monitor unnecessary. The bus transfer cycles are generated in an asynchronous manner.

Destination selection apparatus for a bus oriented computer system

Abstract: In order to carry out data transfer among the subsystems of a bus oriented data processing system, each subsystem is coupled to the bus by a local bus adapter which controls both source and destination aspects of the information transfer Each local bus adapter has a unique "busy" line which may be interrogated by any local bus adapter connected to the bus When a source subsystem wishes to transfer information to a destination subsystem, the source local bus adapter determines from the destination local bus adapter's busy line whether or not the destination subsystem is available to accept the information If the destination subsystem is available, the source local bus adapter requests access to the bus from priority resolution apparatus When the source request is granted, the source local bus adapter issues the message to the bus and also sets the destination local bus adapter's busy line to designate the busy state which indicates to the destination bus adapter that it must prepare to receive a message and also indicates to all subsequently requesting local bus adapters that the particular subsystem to which information just placed on the bus is to be transferred is temporarily not available to receive information from any other local bus adapter When the message has been received by the destination local bus adapter, both the source and destination local bus adapters enter a status cycle to check the integrity of the transmitted message If the message is received intact, both the source and destination local bus adapters complete their individual housekeeping tasks during which the destination local bus adapter turns off its busy line If an error has occurred during the message transmission, the destination subsystem, after the transfer has been retried once, disregards the message and turns off its busy line

Controlling communications between computer devices over common bus

Abstract: A system for controlling communications between a plurality of computer devices via a common bus. The bus includes a multi-conductor data bus and lines for busy, strobe and acknowledge signals. The system involves one universal interface unit associated with each respective computer device. Each device can initiate access to the common bus, through its respective interface unit, on a first-come, first-served basis.

Data processing system comprising input/output processors

Abstract: A data processing system, comprising a central unit, peripheral units, and input/output processors which are connected parallel to a common bus. The said processors centralize the exchanges between a plurality of peripheral units and the store. The data exchanges can be effected in the mode "programmed bus", in which the central unit is the master of the system, or by way of the "multiplex bus", where the exchange is controlled by the input/output processor in word blocks. The interruption system utilizes a second bus which is independent of the first bus, so that the simultaneous transfer of the interruption vectors and data is possible.

Bus switch coupling for series-coupled address bus sections in a microprocessor

Abstract: A microprocessor includes a data bus and an address bus. The address bus has first and second sections coupled together in series by bus switch circuitry. The microprocessor also includes control circuitry for controlling various data transfers in the microprocessor. The bus switch circuitry includes a plurality of MOSFETs each having their gate electrodes coupled to the control circuitry and having their sources and drains coupled to corresponding bus conductors of the first and second sections of the address bus. A program counter, incrementer and other working registers are coupled between the address bus first section and the data bus. An accumulator register and an arithmetic logic unit are coupled between the second section of address bus and the data bus.

Digital control system for heavy goods vehicle - has programmed central memory coupled via four:line bidirectional data bus to control modules coupled to main interface unit

Abstract: The digital control system is used for heavy road vehicle systems where separate computing modules are used for fuel injection, ignition etc. The programmed central memory is coupled to a four line bi-directional data bus. Each computer control module is connected to the bus. An additional bus line provides a status check on which unit is tied to the bus at any instant. All control modules are coupled to a main interface unit providing A/D, D/A conversion etc. The system processing is executed on a byte basis. System operation proceeds with priority assigned to a pre-programmed condition.

Framework of route selection in bus network design

Abstract: The purpose of this study is to establish a framework of route selection in bus network design, based on the proposed functional description and evaluation system. In the proposed framework, the network is classified into residential, activity, and transfer nodes. Routes connecting the transfer nodes serve as the regional system, and other routes constitute the local systems. The evaluation system designed is capable of reflecting both the connectivity of transfer nodes and the accessibility of the residential and activity nodes. To establish the priority of route selection, several attributes were tested against transit use at the neighborhood level. The level of transit service was the sole dominant factor in the traveler's determination of mode choice. Furthermore, the employment activity nodes were significantly correlated with route performance. If the work trips and route performance are given prior consideration, employment serves as a good index during the process of network development. If the provision of accesses to other activities is taken into consideration, employment can also serve as a good indication by connecting those activity nodes to the other elements of the network. This framework will be especially useful when it is integrated in a heuristic algorithm for optimization of network design. A case study was carried out to demonstrate the use of this framework in four stages of bus network development in the Denver area.

Common bus control circuit

Abstract: PURPOSE: To make higher the memory usage efficiency by providing the bus occupying bit in bus commands, and to guarantee the bus usage right with a constant rate for other requesting devices within a unit time by providing the bus cycle occupying counter. COPYRIGHT: (C)1977,JPO&Japio

Multiple access interconnect system

Abstract: A synchronous multiple access interconnect system includes a bus and a plurality of master units each having a six state sequencer coupled to a plurality of serially connected AND gates, the bus and logic to provide signal settling time, generate handshake signals, receive handshake signals, transfer data, resolve contention for the bus between several requesting units and pass control of the bus in an orderly manner from one unit to another. Three signal lines of the bus pass control of the bus from one unit to another.

Simulation of a real time microprocessor network

Abstract: The purpose of this study is to simulate and evaluate the performance of a network of microprocessors as used for a real time control system (1). Specifically the message rates for the inter-processor bus, delays in sending messages and lengths of message input and output queues are to be examined by means of simulation.The system is composed of a distributed network of small, inexpensive microprocessors. The processors can communicate with one another by means of a modular inter-processor bus. This bus modularity permits the system designer the flexibility of adding incremental bus modules to provide for the data capacity and redundancy required by each installation. The low cost of the microprocessors permits the system designer to add processors for both increased computing power and processor redundancy for casualty control and future expansion.

A systems approach of optimal bus network design

Abstract: This report reflects the view that one possible way to improve planning efficiency is to provide the planner with better coordination with decision-makers and with a systematic framework for the bus network design. The purpose of this research is to present a new approach for bus network design. The proposed framework is comprised of four sub-models: attitude model, network generating model, prediction model, and evaluation model. This proposed framework is implemented on a macro-modeling basis. That is, a systems approach of bus network design in which a city is first modeled and bus routes are then fitted into this urban network of nodes and links. This macro-modeling approach is contrary to the street by street modeling of bus routes. Development priorities for various type of bus routes are derived from the socioeconomic characteristics of nodes along the route. In this report, sample applications of this new approach to bus network design are presented using both theoretical viewpoints and empirical analyses. An example of applying the proposed methodology to the Denver area is given to illustrate the operational characteristics of the framework. This study concludes that the proposed approach is a workable one and will be a help to planners in improving the efficiency of transit planning.