Showing papers on "Bus network published in 1978"

System bus arbitration, circuitry and methodology

Abstract: Arbitration of a system bus shared by a plurality of digital processors, input and output devices and memories may be shared in an intelligent and efficient manner by using an arbitration method and an arbiter and bus controller circuit which allows a lower priority processor or user to access the system bus during those times in which a higher priority user of the system bus is not actively accessing the system bus. Thus, without altering the priority assignments among multiple users of a system bus, lower priority users requesting access may be allowed selective and limited access to the system bus during those times in which a higher priority user is in either an idle or halt state or is engaged in utilizing another bus, such as an input/output bus or resident bus.

Apparatus and method for cooperative and concurrent coprocessing of digital information

Abstract: The data processing capacity of a practical semiconductor computer system, having both local and system buses, can be expanded both in degree of complexity and magnitude by providing a method and means for cooperatively and concurrently coprocessing digital information among a plurality of processors sharing the same local bus and collectively accessing the system bus as a system unit. In other words, a central processor has primary control and access to a local bus and may have access to a system or common bus shared among many other processors. Also sharing the local bus with the central processor is a plurality of specialized or dedicated processors which are continuously apprised of or actively monitor the internal operational status and operation then being performed by the central processor. The active monitoring of the activity of the other processors sharing the local bus distinguishes these dedicated processors from conventional direct memory accessing processors. Certain ones of the instructions fetched simultaneously by the central processor and the specialized processor from the system memory are reserved for execution in one of the dedicated processors which then shares the local bus with the central processor by means of communicating through a plurality of signals with respect to the status, mode, arbitration, and control of the local bus.

Current mode data or power bus

Abstract: A current mode data or power bus which provides communication between two or more terminal devices over a common, single-channel medium. The data bus comprises a pair of wires, twisted to form a succession of loops and short-circuited at both ends, together with an arbitrary number of bus couplers, one for each terminal. The bus couplers are formed by separate, disengageable core elements. Each bus coupler is inductively coupled to the twisted wire pair by inserting one or more core legs of the bus coupler through adjacent loops in the twisted wire pair; each wire loop around a core leg then constituting a one-turn transformer winding of the coupler. In this manner, separate terminals can be readily coupled to or decoupled from the current mode data communication bus without the need for making spliced, galvanic connections. This bus configuration is readily adaptable to single or multiphase power transmission. And, in either case, the bus configuration provides excellent electromagnetic interference rejection properties.

Digital bus and control circuitry for data routing and transmission

Abstract: The digital bus is an asynchronous, linear, open-ended digital bus which is coupled to two or more computer/controllers. The bus includes address control circuit lines comprising a bus busy line used by a controller to assert a bus busy signal thereon to gain control of the bus, and to determine if another computer/controller is using the bus, a receiver computer/controller request line used by a controller for requesting permission to send data to another controller, and a receiver computer/controller ready line used by a controller for indicating that that controller is ready to receive data. Data control circuit lines are also provided comprising a data ready line used by a controller for placing a ready-to-send-data signal thereon and a data accept line used by a controller for placing a ready-to-accept-data signal thereon. Also, address bus circuit lines are provided comprising five binary address lines used by a controller for placing an address thereon, which address can have up to five bits. The bus further includes sixteen data bus circuit lines coupled to the two or more controllers. Data to be transferred by a controller is placed on the data circuit lines. A voltage source is coupled to the digital bus lines for pulling up the voltage on all the digital bus lines to the voltage level of the voltage source to make certain that clear signals are provided on the bus and noise problems are avoided. The controllers use the digital bus to asynchronously transfer data and to resolve contention problems between different controllers when they try to gain control of the bus at the same time.

System providing multiple fetch bus cycle operation

Abstract: In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred by the highest priority requesting unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a multiple fetch operation in which the master unit requesting multiple words of information from the slave unit during a first bus transfer cycle may receive such information from the slave unit during a series of later slave generated bus cycles. Logic is provided for enabling any other units to communicate over the common bus during the time between the first cycle and such last cycle during which the slave unit responds, thereby enabling at least two pairs of units to communicate with each other respectively, in an interleaved manner.

Communications bus monitor

Abstract: A monitor provides a continuously active assessment of the performance of a parallel communications bus by continuously comparing the binary level of the bus lines with system-defined levels which should be exhibited when the bus is in an "at rest" condition. Logic circuitry enables bus line logic level comparisons with "at-rest" condition reference values with any one discrepancy providing a latched invalid bus annunciation which is selectively enabled during periods when the bus is sensed to be in the "at-rest" condition.

Information handling unit provided with a self-control type bus utilization unit

Abstract: A plurality of information handling units communicate asynchronously via a common bus using a single signal line. Each information handling unit includes a self-control type bus utilization unit connected to the signal line and operative to connect the common bus to an internal bus of the information handling unit. This unit includes an own name address generator responsive to a bus request signal for outputting the address of the information handling unit, the address being encoded according to that information handling unit's priority among the plurality of information handling units. Transmission gates couple the address to the common bus, and a decision unit compares a signal on the common bus and the address to make a decision based on the assigned priority of the information handling unit to derive a bus grant signal. This signal and a bus available signal on the single signal line are used to derive a signal to drive transmission gates that couple the common bus to the internal bus.

Programmable bus driver isolation

Abstract: A method of and an apparatus for selectively isolating digital data bus drivers from digital data busses for fault recovery and diagnostic purposes. The digital data bus drivers may be either transistor-transistor logic (TTL) or emitter coupled logic (ECL). For TTL digital data bus drivers, the input voltage (V CC ) is supplied via a switching power transistor. For ECL digital data bus drivers, the ground connection (V CC1 ) is made via a switching power transistor. In either case, the switching power transistor is turned on and off in response to one binary bit in an isolation register coupled to the power transistor via an open collector gate or electromechanical switch. By supplying the V CC (for TTL) or V CC1 (for ECL) connection to each digital data bus driver through a switching power transistor and controlling each switching power transistor through a different binary bit in the isolation register, the isolation (or non-isolation) status of each digital data bus driver may be controlled via the isolation register to permit the digital data bus to operate notwithstanding failures effecting the state of one or more of the digital data bus drivers connected to it.

TTL circuits for a 4-valued bus a way to reduce package and interconnections

Abstract: This paper presents voltage mode multi-valued circuits to define a 4-valued bus. Two different versions are presented: TTL circuits for a 4-valued open collector bus, and TTL circuits for a 4-valued p high impedance bus. Some dynamic characteristics are shown. With usual load of a bus, the supplementary delay is less than 55 ns.

Test mode control logic system

Abstract: A logic control system is disclosed for verifying the operability of memory and non-memory data and control paths in both local and remote intersystem link (ISL) units electrically interconnecting a local and remote communication bus in a data processing system. The data processing system may include two or more communication busses each pair of which are electrically interconnected by twin ISL units. The control logic architecture accommodates the receipt of a test mode command from a CPU on a local bus to initiate a test mode operation wherein the memory and non-memory data and control paths of both the local and the remote ISL units are excerised while on-line, and binary coded information received from the local bus is passed through the ISL units, onto the remote bus, and returned to a local bus memory resource for verification. No remote bus resources are used or affected, and the remote ISL unit shall ignore any communications received from any other data processing unit on the remote bus. The remote ISL unit is effectively non-existent to other data processing units on the remote bus.

Test system for data processor

Abstract: PURPOSE: To reduce the semiconductor chip area, by utilizing the inner bus originally present in the central processor of one chip incorporating memory, and making unnecessary te exclusive bus through the connection of input and output port to this. CONSTITUTION: The program instruction in the read only memory 11 constituting the central prcessor is given to the multiplexer 13 having the control input terminal 25 through the bus 12, and this output is set in the instruction register 15 via the bus 14. Next, this instruction is added with the decoder 17 through the bus 16 where it is interpreted, and it is outputted to the output port 19 via the internal bus 18 or is fetched in the bus 18 as data through the input port 21. In testing the unit of this constitution, the input and output port 23 is connected to the bus 18 and the bus 18 is connected to the input side of the multiplexer 13 via the bus 31. Further, the output bus 16 of the register 15 is connected to the bus 18 through the bus 32 and the content of the register 15 is fed to the bus 18. Thus, the buses for exclusive use of instruction and output are made unnecessary. COPYRIGHT: (C)1979,JPO&Japio

Common signal bus system

Abstract: PURPOSE:To attain accurate signal transmission and reception among devices with different interfaces without increasing buses in number, by providing common signal buses of the common controller of an electronic switchboard with a method of setting synchronous bits of each bus interface. CONSTITUTION:Between signal transmitter 2 and signal transmitter 1 differing in bus information array, time-division signal transmission and reception are executed sharing synchronous bit buses S1 to Sn and data bit buses (d1) to (dn) as signal buses. Synchronous-bit transmitting bus driver 11 and synchronous-bit receiving bus receiver 21, provided to transmitter 1 and receiver 2, are provided synchronous bits for respective bus information array kinds as many as the kinds, and a synchronous bit is selected corresponding to the kind of a bus information array. Then, the selected synchronous bits are sent out to buses S1 to Sn to actuate only a group of devices with the same bus information array, so that signal transmission and reception among devices with different interfaces will be made accurate with the number of buses reduced.

Application of the steiner street problem to a more economical data bus

Abstract: A data bus consists of the interconnection of N terminals, each of which is connected to every other terminal. There are three fundamental approaches to the topology of the network: (1) the tee network, for which the connecting nodes coincide with the communicating nodes; (2) the star network, for which there is only one connection node, which may not coincide with a communication node; and (3) the Steiner minimal tree network, for which there can be many nodes, each of which is difficult to locate in the x-y plane. The tee and star approaches are receiving most attention but the third is the only one that economizes on the use of cable (glass fiber waveguide). After a discussion of the tee and star networks, we turn to the Steiner minimal tree network and a method of locating the connecting nodes so that the total amount of cable is minimized.

Circuit for rearranging word bits

Abstract: Circuit includes device coupled to receive a word at its input terminals from an address bus and to gate a rearranged word from its output terminals to a data bus of a controller or processor. The word gated to the data bus has its bits interchanged by coupling each of the input terminals of the device to the output terminals corresponding to the new position of the bit in the rearranged word. The word on the address bus is distinguished from an address by specially coding the high-order lines of the address bus when the lower order lines represent the word.