Showing papers on "Carry flag published in 1977"

System for controlling synchronization in a digital communication system

Abstract: A technique and implementation of generating and supplying synchronization and error checking signals to a serially transmitted data stream includes the generation of flag bytes which define the end boundaries of the serial data stream, an abort character for aborting the transmission of a frame of data in response to certain conditions, and a diagnostic evaluation character inserted into the data stream. In addition, the invention provides a technique for ensuring that the unique binary code by which a flag byte is defined occurs in the transmitted data stream only where intended. The flag code has been chosen to contain a prescribed number of consecutive one bits, (i.e. -- six) flanked by zeroes, and circuitry monitors the contents of a data frame as it is being serialized out for transmission to a remote terminal at times other than during flag transmission. When five consecutive one bits are detected, serializing out of the next bit in the data is interrupted, and a dummy zero bit is inserted prior to the next bit. As a result, the transmitted frame of data will contain no more than five consecutive one bits, except during the flag bytes, (or an abort character) thus ensuring proper synchronization of the end points of the frame. At the receiver terminal, detection and decoding circuitry also monitors the number of consecutive one's in the received data stream. When five consecutive one's are detected, the receiver decoder circuitry checks to see whether the next bit is a dummy zero bit. If the next bit is a zero bit, it is deleted so that the intended data will be correctly reassembled.

Parallelism, Slides, Schemas, and Frames

Abstract: In BT (Brain Theory), we study nets of simultaneously active neurons, and of interacting brain regions. In AI (Artificial Intelligence), we must structure programs for a serial computer. However, the development of a serial algorithm for a function does not preclude the existence of a more efficient parallel algorithm. For example, when adding two numbers, the propagation of the carry bit seems to force seriality. However, a look-ahead adder (see Hill and Peterson (1973) for a textbook treatment) can be built which uses parallelism based on ‘carry look-ahead’ to reduce addition time from the order of n (the length of the numbers) to the order of log n which, in fact, is the best possible (cf. Winograd’s (1965)). Our task here is to examine the ways in which behavior is best expressed in structure, and consider the extent to which we can expect parallelism in that structure. Clearly, the ‘precedence relations’ of the real world — you must walk to the door before you go through it, for example — impose a high-level seriality on the flow of computation. However, within these high-level constraints, we shall see much room for parallel computation.

Carry save adder

Abstract: This carry save adder (CSA) utilizes a pair of edge-triggered flip-flops as output manifesting elements at each CSA bit position, one of these flip-flops being the "sum trigger" which registers the half-sum value (herein called the "sum bit"), and the other flip-flop of the pair being the "carry trigger" which registers the carry value resulting from the binary addition performed by the CSA at that bit position. Each trigger has a latch portion for storing a sum or carry bit value that can be set or changed only at the leading edge of a clock pulse, being stable in the period between clock pulses. A latched sum or carry output bit value at any CSA bit position can be re-entered at any time as input to the same bit position or another CSA bit position, depending upon the operation to be performed (add, left or right shift, or complement). Each trigger also produces an unlatched output sum or carry value known as a "presum" or "precarry" bit. These unlatched bit values may be utilized for trial or test purposes, such as inputs to a lookahead logic network for determining whether a proposed complemental subtraction in a division operation can or cannot be successfully performed.

One's complement subtractive arithmetic unit utilizing two's complement arithmetic circuits

Abstract: The one's complement subtractive arithmetic unit comprises a parallel adder with a connection for providing an end-around carry, from the carry output of the most significant stage to the carry input of the least significant stage. The parallel adder is implemented utilizing multiple bit LSI ALU chips or microprocessor slices that provide group propagate and generate indication signals. Carry look-ahead chips responsive to the group propagate and generate indication signals provide a fast carry arrangement for the arithmetic unit. Circuitry is included to detect when all of the carry propagate indicators are on for providing a signal to the carry input of the parallel adder resulting in the equivalent performance of a one's complement subtractive arithmetic unit.