Showing papers on "Carry flag published in 1983"

Serial comparison flag detector

Abstract: A high speed arrangement for detecting the occurrence of a flag character in a stream of serial digital data signals employs a pattern register in which are stored the bits of the referene flag pattern. As each bit of the serial data is received, it is simultaneously compared by a set of comparators with each of the bits in the flag pattern. The first comparator of the set compares the data bit with the first bit of the flag pattern and each successive comparator compares the data bit with the next successive bit in the pattern. The outputs of the comparators are coupled to corresponding stages of a shift register in the same ordered sequence as the comparators. All the stages of the shift register are arranged to be simultaneously clocked by clock signals. Each stage of the shift register is coupled to the next stage by a gate that permits the shift of a logic bit from the preceding stage to the succeeding stage only when the preceding stage was previously set by a signal from a comparator indicating the occurrence of a match between a data bit and a pattern bit and the gate receives a signal from the next comparator in the set indicating the occurrence of a match between the next data bit and the next pattern bit.

Method and apparatus for calculating the residue of a signed binary number

Abstract: Method and apparatus for calculating the residue of a signed binary number of "n" bits with respect to a given check base m where m=2 b -1. The bits of the binary number excluding the sign bit are partitioned into number segments, each of b bits starting with the least significant bit. If (n-1) is not an even multiple of b, higher order bit positions of the number segment containing the next most significant bit of the binary number are filled with logical zeros. A sign segment of b bits is formed. Both number and sign segments have boundaries. The bit position in the sign segment relative to a sign segment boundary which corresponds to the bit position of the sign bit "s" relative to the nearest boundary of a number segment is filled with a logical zero. All other bit positions of the sign segment are filled with the sign bit. The number and sign segments are applied to carry save adders to reduce the number segments and sign segment to a single sum segment and a single rotated carry segment. A rotated carry segment is a carry segment produced by a carry save adder, the most significant bit of which becomes the least significant bit of the rotated carry segment. The other bits of the carry segment and their significance are increased by one in the rotated carry segment. Carry segments produced by carry save adders of one level are converted to rotated carry segments before being applied to a carry save or full adder of a lower level. The single sum segment and single rotated carry segment produced by the lowest level carry save adder is applied to a one's complement adder. The b bit output of the one's complement adder is the residue of the signed binary number to the check base (2 b -1).

Method for carrying out the Galois field multiplication or division and circuit arrangement for carrying out the method

Abstract: In the error detection and correction of messages transmitted digitally, Galois field multiplications and divisions are required. These can be carried out by means of two read-only memories, an adder and a subtractor, respectively, with the logarithms of the operands. To carry out the operations quickly and inexpensively by means of microcomputers, it is proposed to use a read-only memory with double antilogarithms where the delogarithmating is n -1) must be added to the difference. If n = m, a read-only memory with single stored antilogarithms is used and a full adder is used as adder, the carry bit being added or subtracted for correcting the modulus.

Digital multiplier and method for adding partial products in a digital multiplier

Abstract: A complement carry technique and a staged skipping technique are employed for multipliers using four or more stages of carry save adders (A1....A7), to allow slower bits (S41) to skip past a stage while faster bits (C40) must go through that stage, thereby speeding up the multiplier's overall speed of operation. The complement carry technique minimizes hardware by allowing sums and carries to be generated by the carry save adders (A1....A7) in either a true or a complement form. The skip technique takes advantage of the fact that the generation of a carry bit is faster than the generation of a sum bit. In the case of a four stage carry save adder designed for a multiplier, the skip technique reduces the number of circuit delays from the existing eight to the improved seven, without the addition of any hardware. Thus, the technique can result in a speed improvement for a multiplier.

Detecting method for exception of floating decimal point instruction

Abstract: PURPOSE:To decrease the operation time, by checking the generation of overflow only when the specified carry reduced to ''1'' and that of underflow only when reduced to ''0'', at the operation of the exponential part CONSTITUTION:Signs and indexes S1, S2, C1 and C2 of multipliers and multiplicands read out from a specified address of a local storage WK at an operating circuit are set to registers REGa and REGb, these are added at an arithmetic section ALU, and the result is stored in the storage WK In this case, the signs S1 and S2 are stored to the indexes C1 and C2 in the status register ASR of the ALU A branch instructin observes the carry bit of the register ASR and changes the run sequence of the microprogram according to ''1'' and ''0'' When the carry bit is on-state, only the overflow check is made and when off-state, only the underflow check is made

Instrumentation circuit for digital picture

Abstract: PURPOSE:To prevent a picture signal data from an area error due to color blurring or noise components, by providing the titled circuit with an area error detecting circuit to simultaneously detect and discriminate the overflow and under flow of a two-stage adder adding picture signals. CONSTITUTION:Data H, J (J is a negative number) are inputted to a different code input adder 2 to be operated. The status of a carry bit K is transmitted to an area error preventing circuit 5. The added result is inputted to a superposing circuit 3 and a fixed value is added to the result. The status of a carry bit L at the addition in the superposing circuit 3 is also detected to the area error detecting circuit 5. The circuit 5 discriminates whether the final data of the operation are variable, overflowed or underflowed and outputs a control signal M to a maximum/minimum detecting circuit 4.