Showing papers on "Carry flag published in 1986"

N-bit carry select adder circuit with double carry select generation

Abstract: A circuit for adding two N-bit binary numbers with an input carry bit, where N is an integer, by the carry select technique is provided. A ranked ordered plurality of section adders function in conjunction with rank ordered carry select logic circuits to initially provide two sum bits and two output carry bits for each bit position corresponding to carry input bits of zero and one, respectively. The section adders comprise full adders and are divided into at least two ranked groups in which sum bits are concurrently calculated in each group. Each full adder concurrently provides two sum bits for each rank ordered output sum bit. The rank ordered carry select logic circuits sequentially provide carry select bits which are used by the full adders to select one of the two sum bits as the output sum bit. Two output carry bits are concurrently provided by each group. One of the two output carry bits of the lowest ranked group is provided as a half carry output bit in response to the carry input bit. One of the two output carry bits of the highest ranked group is provided as the sum output carry bit in response to the half carry bit of the lower ranked group.

Apparatus for bit-parallel addition of binary numbers

Abstract: In an arrangement for the bit-parallel addition of binary numbers in two's complement form, a series of adders (AD i ) are provided to receive inputs for binary bits of equivalent significance and to emit intermediate sum and carry words which are combined to form result sum words. For the correction of overflow errors, the carry bit of the adder (AD n-2 ) having the second highest significance is replaced by the carry bit of the most significant adder (AD n-1 ) and, when the carry bits of the two most significant adders (AD n-1 , AD n-2 ) are unequal, the intermediate sum bit of the most significant adder (AD n-1 ) is replaced by its carry bit.

Process selecting system

Abstract: PURPOSE:To perform processing selection with a small number of steps by using a subroutine selected among plural ones as bit information and producing the jump/reset addresses from the time series output of information on the subroutine selection bit and a table. CONSTITUTION:A shift register 1 stores a bit corresponding to the selected processing subroutine in the form of '1'. When a jump instruction JSX is execut ed at an address 1,000, an address 1,002 of a processing subroutine 1 following the JSX is stored in a pointer register 6. The high-order four bits of a counter 3 are all set at '1' owing to the generation of the JSX. Then the register 1 is shifted left by two bits and stopped when a carry bit 2 is set at '1'. Then only the high-order four bits of the counter 3 are counted up and supplied to an adder 7 to be added with the value of the pointer 6. As a result, the head address of a subroutine 2 of an address 1,004 is supplied to a program counter 9. Thus the subroutine 2 is processed.

Inter-picture element arithmetic circuit

Abstract: PURPOSE:To increase the inter-picture element arithmetic processing time by using a clamping circuit which selects and delivers the arithmetic result of an arithmetic logical operation ALU or the clamp data as the output data and also delivers the complement signal. CONSTITUTION:A decoding circuit 20 in a clamping circuit 14 decodes the arithmetic mode information M of an ALU13, a carry bit C, the highest bit A of the arithmetic result, a sign bit S of the 2nd picture data held by a register 12 and the expression condition N and delivers a complement signal 15 as well as selection control signal 22-24 to be sent to a selector 21. The selector 21 selects either one of the arithmetic result l of the ALU13, the over-clamp data (m) containing all bits set at logic 1 and the under-clamp data (n) containing all bits set at logic 0. A selector 17 selects and delivers the output data given from a complement circuit 16 or the coupled information (C+q) of the carry bit C given from the ALU13 and a bit (q) excluding the lower bit of the result l as the 3rd picture data.

Automatic switching device of film sensitivity

Abstract: PURPOSE:To decide automatically whether a film sensitivity can be read or not by providing a film sensitivity detecting means, a means for adding 1 bit to its signal, and a detecting means, etc. CONSTITUTION:A titled device is constituted of a microcomputer 14, a photometric circuit 15, a pulse motor driving circuit 16, a sector 18 and switch groups DX1-DX5, DX6-DX9, etc. In this state, when a film conforming the International Standardization Organization (ISO) is loaded, a contact of a switch corresponding to a sensitivity contact piece of a cartridge among the comman contact DX1 and the switches DX2-DX5 becomes on, other contact maintains an off-state, a parallel signal of 5 bits consisting of an L signal and an H signal is generated. In this case, a computer 14 reads only a signal of 4 bits by the switches DX2-DX5, and at the same time, adds an L signal of 1 bit. By adding this 1 bit, a carry flag is not generated, therefore, a film conforming to the ISO is decided, and a signal from the switches DX2-DX5 is read.

Arithmetic and logic unit

Abstract: An arithmetic and logic unit ("ALU") of a microprocessor is subdivided into two blocks corresponding respectively to bits 0-15 and 16-31, the first block being of the type with simple carry propagation ("manchester carry ripple") and the second being of the type with carry selection ("carry select"), each of the blocks itself being subdivided into sub-blocks each of four bits, sub blocks each equipped with a carry skip device ("carry skip") relating to the sub block With each four bit sub-block is associated a circuit (LOOBIT, LOOBIS) for carrying out the carry skip and regenerating the levels