Showing papers on "Carry flag published in 1988"

Content addressable memory with flag storage to indicate memory state

Abstract: A content addressable memory device capable of correct retrieval operation comprises a flag bit column (12) provided in a memory cell array. The flag bit column (12) stores a flag signal indicating whether a word is in a data written state or an empty state for each word in a data array (2). In the retrieval operation, the data written in the data array (2) and a flag bit column (12) are simultaneously retrieved, providing a correct retrieval result. In addition, since the flag bit column (12) is provided in the memory cell array, it can be controlled in a manner similar to controlling the data array (2).

Apparatus and method for floating point normalization prediction

Abstract: The invention is directed to an apparatus and method for predicting the number of bits which must be taken into account to normalize the result of a floating point addition or subtraction. The apparatus and method employ: a low precision floating point adder/subtractor, a priority encoder that determines the position of the most significant non-zero bit to generate the normalization amount and preround logic which pre-shifts a rounding bit in the opposite direction of normalization. The method and apparatus operate in parallel with a full precision floating point adder to eliminate the need for a full-precision floating point normalization calculation and rounding computation in most circumstances. The normalization amount for successful low-precision floating-point addition/subtraction is calculated by the time the full-precision floating-point addition/subtraction stage occurs. Moreover, the pre-round logic supplies a carry bit to the full-precision adder/subtractor thus saving the time associated with a full-precision rounding bit addition. Thus, this low-precision floating-point addition/subtraction technique results in a significant enhancement of performance in floating-point addition/subtraction.

Arithmetic-logic operation unit having high-order and low-order processing sections and selectors for control of carry flag transfer therebetween

Abstract: Two arithmetic logic units (ALUs) are provided, one a high-order side and another on a low-order side such that data on the high-order side and on low-order side, output from each of a source data register and a destination data register, are respectively supplied to the ALUs to be operated on thereby. There is provided a selector circuit on the output side of the source data register, which selector circuit operates to deliver the data on the high-order side and that on the low-order side from the source data register selectively to the ALU on the high-order side and that on the low-order side according to the operating mode. Carry outputs from each of the ALUs are input to a first selector and one is selected according to the operating mode and stored in a carry flag register. The output of the carry flag register and the carry output of the ALU on the low-order side are input to a second selector whereby one output thereof is selected according to the operating mode and input to the ALU on the high-order side as the carry input thereto, and also, the output of the carry flag register is supplied to the ALU on the low-order side as the carry input thereto.

Arithmetic processor performing mask and trap operations for exceptions

Abstract: A floating-point arithmetic processor performs a MASK or TRAP operation in response to occurrence of an exception. This processor includes a first flag which is set when the exception occurs, a second flag storing first data designating the MASK operation or second data designating the TRAP operation. A third flag is set when the first flag is set and the second flag is storing the second data. A controller produces a default value in response to the occurrence of the exception. The processor also includes a destination register, which is accessible by a central processing unit (CPU), and a transfer gate circuit which takes an open state to allow the default value to be stored into the destination register when the third flag is not set and a closed state to inhibit the default value to be stored into the destination register when the third flag is set.

Address sequence generation by means of reverse carry addition

Abstract: An apparatus and method is disclosed for generating a bit reversed sequence. The apparatus includes a reverse addition means for adding binary words in most significant to least significant bit order with the overflow or carry bit propagated to the left. The invention is used to generate a bit reversed address and/or an address sequence that is mapped into a "closed" space.

Adder having means for reducing propagation time of carry bit

Abstract: An adder has first through third switching circuits, a logic circuit and an adding circuit part. The first switching circuit is coupled between a carry bit input terminal and a carry bit output terminal. The second switching circuit is coupled between a first power source voltage and the carry bit output terminal, and the third switching circuit is coupled between a second power source voltage and the carry bit output terminal. The logic circuit controls the ON/OFF states of the first through third switching circuits so that only one switching circuit is turned ON responsive to two binary values which are to be added in the adding circuit part. The propagation time of a carry bit signal from the carry bit input terminal to the carry bit output terminal is constant regardless of the number of bits of the adding circuit part.

Signal generator for circular addressing

Abstract: A signal generator provides circular addressing, i.e., performs basic modulo boundary indexing, which includes both positive and negative addressing, by adding an increment to a base register until a modulo boundary is reached without permitting the carry bit to pro­ pagate but instead resetting the address back to its lowest value. More particularly, the invention provides a signal generator which includes an adder having base address signals applied thereto from one of a plurality of registers and having an operand such as signals from an instruction data register (IDR) also applied thereto. Selected most significant bits from the output of the adder are applied to the input of a modulo mask function unit. Also applied to the input of the modulo mask function is a number of most significant bits of the base address signal. The carry bit from the adder is also applied to the input of the modulo mask function unit. The desired modulo is selected under the control of a decoder coupled to the modulo mask function unit. The output from the modulo mask function unit is applied to a common address register, along with the remaining least significant bits from the adder. In a preferred embodiment of the invention, the modulo mask function unit includes a plurality of passgates connected between the adder and the common address register and between the source of the most significant bits of the base address signals and the common address register.

Method and apparatus for a parallel carry generation adder

Abstract: The parallel carry generator calculates the carry for a m bit number within log 2 n+1 gate delays where n is smallest binary ordered number greater than or equal to m. Thus in the parallel carry generation adder of the present invention, the sum is calculated in log 2 n+2 gate delays. Thus, a 32 bit carry computation can be performed in as little as 6 gate delays. This is achieved by breaking down the 32 bit word according to binary ordered values and cascading portions of the calculations required wherein the carry generated for the most significant bit of the lower binary ordered group is used to calculate the carrys for the bits in next higher ordered group. By ordering the bits and the logic circuitry in this manner, the amount of gate delays to perform the carry calculation is minimized without excessively increasing the amount of logic.

Method of identifying flag bits

Abstract: A technique for determining and resetting one or more flags in a digital word in memory in which the flags comprise added bits in known locations different from any of the magnitude bits in the word. A sign bit is included and a flag is set by making its bit value differ from that of the sign bit. A digital word from the memory is AND'd with a bit mask to check the flag bit location. A parity routine is run to determine whether the flag bit is set, and if so, the memory location of the word and the type of flag is recorded. The word with the flag bit set is XOR'd with another bit mask to reset the flag bit so that the word may be returned to its memory location with the flag reset.

Arithmetic logic system capable of checking carry look-ahead circuit

Abstract: An arithmetic logic system includes a plurality of arithmetic logic units for processing data composed of a corresponding number of bits and having a path for transferring a carry through the respective arithmetic logic units, and a carry look-ahead circuit provided in parallel to the carry transfer path and having inputs respectively connected to the arithmetic logic units for generating a carry look-ahead signal when a carrry look-ahead condition is realized. A carry signal output is connected to a most upstream end of the carry transfer path, and a first transfer gate is connected at its one end to the carry signal output and at its other end to a predetermined voltage. The first transfer gate operates in response to the carry look-ahead signal so as to connect the carry signal output to the predetermined voltage. A second transfer gate is connected between the carry signal output and the most upstream end of the carry transfer path. This second tranfer gate operates in response to a test mode signal to isolate the carry signal output from the carry transfer path so that the carry is transferred through only the carry look-ahead circuit. Therefore, if any failure occurs in the carry look-ahead circuit, an error will be generated in the result of operation on the arithmetic logic system.

Flag generating circuit

Abstract: PURPOSE:To detect at high speed the all '0' and all '1' of the arithmetic result by carrying out simultaneously plural pairs of logic operations for four bits adjacent to each other of two arithmetic input data A and B. CONSTITUTION:An addend and an augend are stored in an X register 114 and a Y register 115 of an arithmetic unit 100 and an arithmetic operation is carried out. The augend is supplied to a complement circuit 112 from the register 115 for the execution of adding/subtracting operations. An adder 111 has an carry transmission circuit and holds a generated carry flag in a carry holding FF. A zero flag generating circuit 110 detects whether the arithmetic result of the adder 111 is is equal to all '0' or not before reception of the output result of the adder 111. Then the circuit 110 is actuated independently of the adder 111 so that a zero flag is obtained earlier than the arithmetic result.

Elemental operator, especially for a cascade-type multiplier

Abstract: of EP01127681. An elementary operator for combining a first digital input signal of at least n bits (SX, X) with a second digital input signal comprising a first and a second bit (Y2j-1 , Y2j ) in order to obtain an output digital signal with an output carry bit, said operator comprising : - computing means (108) for complementing (~X) the first signal in order to offset it one step to the left (2X) while losing the high value bit and to complement (~2~X) this first offset signal ; - a first exclusive OR-gate (112) in order to receive the first and the second bits (Y2j-1 , Y2j ) of the second digital signal and to apply a first function bit ; - an n bit adder (110) ; - a first register (103) for storing the first signal and for applying it to the computing means (108) for the first signal, characterized in that it comprises : - a third input digital signal of n bits (RIj-1 ) ; - a first 4 to 1 multiplexer (109) to select a signal between the first signal, the first signal in an inverted form, the first signal in an offset form, and the first signal in an offset and inverted form, under the control of the third bit of the third signal and of the first function bit, and to supply the n high value bits of the selected signal ; - a second exclusive OR-gate (115) to receive the second and the third bits of the third signal and to supply a second function bit ; - a second 2 to 1 multiplexer (111) to select a signal between the second signal and the sum supplied by the adder under the control of either of the two function bits and to supply the fourth signal ; - in that the second digital furthermore comprises a third bit (Y2j+1 ) and an input carry bit, in that the adder is adapted to cause the addition of the third digital signal and of the signal selected by the first multiplexer with one input carry bit and to supply the sum of these signals and the output carry bit - and in that in order to store the first signal and the first register (103) supplies a fifth digital output signal comprising the n high value bits of the first signal.