Showing papers on "Carry flag published in 1991"

An arithmetic operation unit having bit inversion function

Abstract: A bit-inversion arithmetic operation unit comprises a first carry signal line for propagating a carry signal from a more significant bit position side to a less significant bit position side, and a second carry signal line for propagating a carry signal from a less significant bit position side to a more significant bit position side. A common logic circuit performs at least a portion of a carry control including a carry propagation of the first and second carry signals and a carry generation. A switching and logic circuit responds to a required arithmetic operation mode so as to control the common logic circuit and to perform the remaining portion of the carry control including the carry propagation of the first and second carry signals and the carry generation.

Radix aligner for floating point addition and subtraction

Abstract: In a hardware floating point adder, each operand exponent is logically divided into fields. The corresponding fields of each exponent are input to a separate shift logic circuit which determines a relative amount to shift the operand mantissa without reference to any carry bit from a lower order field. Both mantissas are potentially shifted, each by one or more shift logic circuit outputs, making it possible to perform some of the shifts simultaneously. Using 11 bit exponents in accordance with ANSI/IEEE Standard 754-1985, double format for 64-bit numbers, operand registers are logically divided into: field #3, consisting the lowest two order bits; field #2 consisting of the next lowest two order bits after the first two; and field #1 consisting of the highest 7 order bits. The shift logic circuit for field #3 shifts and Operand A mantissa, right or left, 0, 1, 2 or 3 bits. The shift logic circuit for field #2 simultaneously shifts an Operand B mantissa, right or left, 0, 4, 8 or 12 bits. The shift logic circuits for field #1 shifts and Operand B mantissa, right or left, 0, 16, 32, 48 or 64 bits; this shift is performed after the shift from field #2. The cumulative shifts performed above effect a relative shift of the two mantissas by the correct amount. The mantissas are then added/subtracted in the normal manner, and shift adjusted after the addition/subtraction.

Electronic circuit and method for half adder logic

Abstract: An electronic half adder circuit wherein an entire word of either 16 or 32 bits is divided into stages, carry is rippled within each stage and look-ahead carry is computed between the stages, having a dual gate look-ahead carry circuit for propagating a look-ahead carry bit between said stages. This is also a processor system. The system includes: memory for storing program instructions; a processor coupled to the memory for receiving predetermined ones of the program instructions; the processor comprises: an arithmetic unit; control circuitry for controlling the arithmetic unit in response to selected ones of the predetermined program instructions; a counter coupled to the control circuitry comprising half adder circuitry wherein a dual gate look-ahead carry circuit for propagates a look-ahead carry bit between the stages. Additionally, this is a half adder circuit for a device formed on a semiconductor substrate wherein the carry look-ahead circuit has two gates so that the layout space on the semiconductor is minimized and the speed of a signal through the dual gate carry look-ahead circuit is increased. Other devices, systems and methods are also disclosed.

Method and apparatus for negating an operand

Abstract: A multiplier system 12 is disclosed which provides for the negation of an operand stored in an operand register 14. When a negative operand must be loaded into a partial product generator 26, a carry bit is selectively generated in carry logic 44 and a selected bit or bits within the partial product is set to zero. During a subsequent pass through the multiplier system 12, a bit is added at a block 46 to provide for the addition of the required quantity for the negation of the operand.

High speed full adder and method

Abstract: A high-speed current mode 2-bit full adder using ripple carry with two full adders using three-levels of series gating, a bandgap reference voltage generator, two sum out buffers, and a carry out buffer. The method for the addition of an input carry bit and two 2-bit input bytes uses a logic circuit satisfying Boolean expressions SUM=ABC+AB'C'+A'B'C+A'BC' and C OUT =BC+AC+AB, where first 2-bit input byte A 1 B 1 and carry in byte C IN produce SUM equal to first bit sum S 1 and an intermediate carry out bit at two voltage levels, C 2 , and C 3 to facilitate processing. Second 2-bit byte A 2 B 2 and an intermediate carry out bit at C 2 and C 3 , input to the bit 2 full adder, produce SUM equal to secondd bit sum S 2 and final carry out bit C OUT . Each sum function uses only one current source to reduce components, lower power consumption, and improve efficiency.

Comb filter including a data overflow monitor, and a radio including the same

Abstract: A monitor (102) is suitable for monitoring the data integrity of a comb filter (101). Generally, the filter will include at least one differencer stage, at least one buffer stage, and at least one integrator stage, including an output integrator stage (500). The output integrator stage will include a most-significant input bit (150) ("I"), a most-significant output bit (130) ("O"), and a carry bit (140) ("C"). In one embodiment, the monitor includes a detector (600) for detecting an overflow condition in the filter based on the equation (inverse C) * (O) * (I)+(C) * (inverse O) * (inverse I). The monitor also includes a waveform generator (700) that, in response to the occurrence of an overflow condition, generates a resetting waveform (170) of a predetermined shape and time duration, that is then coupled to the resetting terminals of all stages in the filter.

Memory circuit with self-diagnostic function

Abstract: PURPOSE:To execute the diagnosis without interposing a diagnostic device and to shorten the rise time by providing a self-diagnostic function in a memory circuit CONSTITUTION:By an initialize signal S2, a selection control signal S3 from a selection control flag 4 is activated and becomes a diagnostic mode, and an address selecting circuit 10 and selecting circuits 11, 13 etc, are controlled Subsequently, diagnostic address data counted up successively from zero by a +1 counter from a diagnostic address register 2 is selected by the circuit 10 and supplied to a memory 1, diagnostic data is written in the memory 1 through the circuit 11, and simultaneously, the diagnostic data is supplied to an output data register 6 through the circuit 13, a read-out output of the memory 1 and an output of the register 6 are brought to coincidence/discrepancy detection and the diagnosis is executed When this diagnosis is repeated with regard to all addresses, a flag 4 is reset by a carry flag 15 of the register 2, and since a self-diagnostic function is provided in a memory circuit, the diagnosis is executed without interposing a diagnostic device and the rise time of the device is shortened

Timer control method for multiprocessor system

Abstract: PURPOSE:To execute a read clock instruction, with which each processor reads the value of a common timer means, at high speed by providing the common timer means to be shared by the plural processors, high-order register, low-order register and updating means. CONSTITUTION:When the read clock instruction is executed at first, a common timer 4 is read. The read value is stored in a high-order register 5 and a low- order register 6 and after the value is stored, the contents of the register 6 are updated by an updating circuit 7. Next, as the result of the updating, a carry flag 8 is set and when the read clock instruction is executed after second operation, the flag 8 is checked. As the result of the check, when the flag 8 is 0, the register 5 and register 6 are read. On the other hand, when the flag 8 is 1, the timer 4 is read and the read value is stored in the register 5 and register 6. Thus, each processor 1 can execute the read clock instruction, with which the value of the timer 4 is read, at high speed according to the state of a carry and the performance of a computer system can be improved.