Showing papers on "Carry flag published in 2008"

Risc processor and its register flag bit processing method

Abstract: The present invention discloses a RISC processor and a method of processing flag bits of a register in the RISC processor. Said RISC processor comprises a physical register stack, an operating component connected to the physical register stack and an decoder connected to the operating component; the physical register stack comprises an emulation flag register for emulating to realize flag bits of a flag register in a CISC processor; the operating component comprises a flag read-write module for reading and writing the values of the flag bits of the emulation flag register. The operating component further comprises an operating controller for performing an operation control according to the values of the flag bits of the emulation flag register when the RISC processor is in the working mode of X86 virtual machine during an operation process.

Arithmetic processing apparatus and arithmetic processing method

Abstract: In an arithmetic processing apparatus, a dividing unit divides a second bit string into a low-order bit part having a bit width equal to a first bit width and a high-order bit part which is higher than the low-order bit part, a first arithmetic unit performs arithmetic operations for a carry to and a borrow from the high-order bit part; and a second arithmetic unit performs addition of absolute values of the low-order bit part and the first bit string. Finally, a selecting unit selects an output of the first arithmetic unit from among an arithmetic operation result with a carry, an arithmetic operation result with a borrow, and the high-order bit part itself, according to information about the high-order bit part, sign information of the first bit string and the second bit string, and an intermediate result of the addition of the absolute values by the second arithmetic unit.

Mathematics addition and subtraction exercising device

Abstract: The utility model provides an addition and subtraction math trainer which is used for improving the math operation ability and speed of the student and is convenient for the student to practise math exercises. The math trainer comprises of a shell, a numeral window, an answer window, a math symbol window, an operation window, an operation button which is arranged in the operation window in a slipping way, a rolling numeral strip, etc., wherein, the numbers on the numeral strip are successively displayed in the numeral window and the answer window by operating the operation button, simultaneously, and a carry bit device is additionally arranged at the upper part of the shell. When in use, the carry bit device can display the carry bit code only by dialing the carry bit code wheel, and has simple use procedure; the students do not need to memorize the carry bit numbers all the time when the students carry out long number math operation, the students can effectively deepen the understanding of the carry bit operation, and the students familiarize and grasp the long number math addition and subtraction operation better, the study efficiency of the students is improved, and better study efficiency is achieved.

Semiconductor integrated circuit in in a carry computation network having a logic blocks which are dynamically reconfigurable

Abstract: There is provided a semiconductor integrated circuit including: a plurality of first logic blocks which are reconfigurable, the plurality of first logic blocks inputting data of a first bit width and performing computation; a first network connecting the plurality of first logic blocks in a dynamically reconfigurable manner; a plurality of second logic blocks inputting data of a second bit width different from the first bit width and performing computation; a second network connected to outputs of the plurality of second logic blocks; and a third network connecting a carry bit output of a computing unit included in the first logic block to an input of a computing unit included in the second logic block in a dynamically reconfigurable manner.

Instruction execution processor

Abstract: PROBLEM TO BE SOLVED: To suppress hazards in pipeline processing through a simple structure. SOLUTION: An instruction set (consisting of an instruction code and a skip condition) fetched to an instruction register 2 is decoded by an instruction decoder, and executed by an execution unit 5. When the instruction is an arithmetic instruction, the execution unit 5 outputs the execution result of the instruction as an arithmetic result flag (carry flag, etc.), and stores the flag in a flag register 6. The arithmetic result flag is compared with a skip condition bit in the instruction set by a matching circuit 8, and when the both are matched, a skip flag is set in a flip-flop 9. According to this, the execution unit 5 stops execution of the following instruction. Consequently, by using an instruction with skip function instead of a conditioned branch instruction, establishment of a branching condition by the execution result of the conditioned branch instruction can be performed without stoppage of pipeline processing. COPYRIGHT: (C)2008,JPO&INPIT