Showing papers on "Carry flag published in 2009"

Semiconductor integrated circuit

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of improving bit accuracy when performing accumulation or product sum operations or the like and preventing the generation of waste resources SOLUTION: The semiconductor integrated circuit includes: a plurality of reconfigurable first logic blocks 111 for inputting data of a first bit width and performing computation; a first network 112 connecting the plurality of first logic blocks in a dynamically reconfigurable manner; a plurality of second logic blocks 121 for inputting data of a second bit width different from the first bit width and performing computation; a second network 122 connected to outputs of the plurality of second logic blocks; and a third network 120 connecting a carry bit output of a computing unit included in the first logic block to an input of a computing unit included in the second logic block in a dynamically reconfigurable manner COPYRIGHT: (C)2010,JPO&INPIT

Rotate instructions that complete execution without reading carry flag

Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

Method of forcing 1's and inverting sum in an adder without incurring timing delay

Abstract: A summing circuit for an adder decodes control signals to determine that the result should be manipulated, and generates a half-sum output which is used to produce a manipulated result based on the control signals. The half-sum output is combined with a previous carry bit to complete the sum operation. The control signals can invert the adder result, or force the result to be all 1's. These functions can be effectuated in a 3-way multiplexer that combines the operand inputs and control signals. For inversion, two separate logic circuits produce true and complement half-sums in parallel, and the appropriate half-sum is selected for the half-sum output. For a result of all 1's, a force_1 control signal pulls the half-sum output node to electrical ground and the final output is manipulated by gating the carry signals with the force_1 signal. The two functions are implemented without introducing additional delay.

Multiplication Instruction for Which Execution Completes Without Writing a Carry Flag

Abstract: A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.

Parallel computation apparatus

Abstract: PROBLEM TO BE SOLVED: To provide a parallel computation apparatus that facilitates executing a structured program having a plurality of nests. SOLUTION: In the parallel computation apparatus, each of a plurality of arithmetic processors performs parallel arithmetic processing by use of a plurality of subprocessors. The subprocessor (SPE) 102A includes: an ALU (Arithmetic and Logic Unit) 95A performing arithmetic processing of input data based on control instructions; a G flag stack 11 sequentially accumulating flag information based on results performed with the arithmetic processing; and an SPE control unit 199A making the ALU 95A perform the arithmetic processing based on composition flag information composed with the accumulated flag information by a composition part 19. The subprocessor 102B includes an ALU 95B performing the arithmetic processing of input data based on the control instructions; and an SPE control unit 199B making the ALU 95B perform the arithmetic processing based on the composition flag composed by the composition part 19. COPYRIGHT: (C)2011,JPO&INPIT

Microprocessor extended instruction set precision mode

Abstract: A method and apparatus to gain additional functionality of a microprocessor by adding an extended instruction set mode. In this mode, the result of executing an instruction may be changed without changing the instruction itself. In the extended instruction set mode, there is an increase to the number of bits of precision when executing the plus instruction. An additional bit position is added to the program counter register. When this bit is set, the microprocessor is in extended instruction set mode. In addition, a new one bit latch is provided. The latch may be changed only when the microprocessor is in extended instruction set mode. The latch is defined as holding a true carry bit. A significant bit of a register holding a sum is saved in the carry latch at the end of the plus instruction.