Showing papers on "Carry flag published in 2012"

Thermometer Code Based Modular Arithmetic

Abstract: This paper presents a novel approach to perform modular arithmetic addition and subtraction using base-1 thermometer code data format for operands corresponding to the residues of the same modulus. Two n-bit thermometer code operands are first concatenated and logically shifted to produce a normalized 2n-bit thermometer code intermediate sum. Modulo operation is then applied to this 2n-bit intermediate sum to produce an n-bit datum corresponding to the modular sum of the two input operands. This approach greatly simplifies the modulo addition operation by eliminating the carry bit propagation during the arithmetic operation encountered when using the conventional base-2 binary code data format. It also enables practical applications of modular arithmetic for signal processing algorithms in a very efficient way. Circuit for implementing the modular arithmetic units using multiplexers and basic logic gates are also described in this paper.

Fusion processing device and method for floating-point number multiplication-addition device

Abstract: The invention provides a fusion processing device and a fusion processing method for a floating-point number multiplication-addition device. The method comprises the following steps of: inputting real parts and imaginary parts of a multiplier and a multiplicand of a floating point complex number into floating-point multiplication modules M0 and M1, and performing floating-point multiplication operation, wherein output results present products by using a carry bit and a partial sum; inputting the products into a floating-point addition module A2, and performing floating-point addition operation, wherein the output results present addition operation by using the carry bit and the partial sum; inputting the output results which present the addition operation into floating-point addition modules A0 and A1 simultaneously; inputting addends input from the outside into the floating-point addition modules A0 and A1, and performing floating-point addition operation; and outputting operation results. The device and the method can be better applied to butterfly computation of Fourier transform; and by the device and the method, operation steps can be simplified, hardware resources are easy to save, and the multiplication-addition operation of the floating point complex number is realized by less resources.

Method to implement a binary flag in flash memory

Abstract: A system and method for changing a state of a binary flag in a flash memory. The method defines a cell segment including a predetermined number of bits as the binary flag, where each bit is converted to a logical 1 when the memory is erased. The method also defines that an even number of logical 1 bits in the flash cell segment is an even parity and an odd number of logical 1 bits in the flash cell segment is an odd parity, and defines whether an even parity is an ON state of the binary flag or an odd parity is the ON state of the binary flag. The method changes the parity of the binary flag by writing one of the bits in the flash cell segment from a logical 1 to a logical 0 to change the state of the flag.

DNA Addition Algorithm Based on Molecular Beacon

Abstract: A new DNA computing model to realize binary integer additions based on molecular beacon is described in this paper. The binary 0 and 1 are represented by two different fluorescent states of a molecular beacon since its two different structures. By designing sequences of molecular beacons skillfully, and using the relationship between each two corresponding bits and their result and carry bit of two operational numbers, the computing process to compute each two corresponding bits of the binary numbers is simulated in the test tube. Finally, the results can be read only by detecting whether the fluorescence in tube emits. The result of the experiment shows that the algorithm is simple and convenient, and the algorithm provides a new idea for DNA computing to realize arithmetic operations

Absolute position encoder for Hall multiple rings

Abstract: The invention relates to an absolute position encoder for Hall multiple rings, which comprises a housing and a circuit board. The absolute position encoder is characterized in that multiple levels of counting gears in carry bit connection are installed in the housing, and each counting gear consists of a gear body and a carry bit gear. The carry bit gear is installed between the adjacent counting gears and connected with the carry bit gear of the primary level counting gear and the gear body of of the next level counting gear. An axle hole or an axle extension structure is arranged at the bottom end of the first level counting gear. A piece of magnetic steel is fixedly installed in the middle position at the top end of each of the multiple levels of counting gears. A hall sensor is installed on the circuit board in a position opposite to the magnetic steel. Compared with the prior art, the encoder is low in processing difficulty and simple and convenient to assemble. The encoder has good adaptability to severe working environment. The output signal is relatively regular and an amplifying and shaping circuit is omitted. Therefore, the encoder is provided with less circuit elements and simplifies the circuit structure. The carry bit structures among the levels are compactly connected and the whole structure is small in size. Each position corresponds to a determined and unique data signal so as to realize encoding in the absolute position.