Showing papers on "Carry-lookahead adder published in 2012"

Area, Delay And Power Comparison Of Adder Topologies

Abstract: Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. This paper presents the pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area. The adder topology used in this work are ripple carry adder, carry lookahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder and carry bypass adder. The module functionality and performance issues like area, power dissipation and propagation delay are analyzed at 0.12 µm 6metal layer CMOS technology using microwind tool.

Memristor based carry lookahead adder architectures

Abstract: In this paper, the material implication logic gate has been realized using memristors. A memristor can be used as a logic gate or a latch which is known as ‘stateful logic’ [8]. All logic gate realizations have been presented using material implication. A new realization of two carry lookahead adder architectures based on material implication has been proposed. A performance comparison with conventional ripple carry adder based on material implication has been performed.

A Fast 64-bit hybrid adder design in 90nm CMOS process

Abstract: This paper presents a novel multiplexer-based carry-skip algorithm for hybrid adder design based on the parallel-prefix computation technique. The hybrid adder combines both carry-lookahead and multiplexer-based carry-skip architectures to speed up the performance. The driving capability of the critical path is enhanced to boost the speed, while optimizing both area and power in the non-critical paths. Experimental results show that the proposed 64-bit hybrid adder achieves low cost (46 × 210 um2), low power (2.82 mW), and high speed (246.5 ps), where the UMC 90 nm CMOS process is simulated with 1.0V supply voltage.

Design and implementation of a high performance multiplier using HDL

Abstract: This paper presents an area efficient implementation of a high performance parallel multiplier. Radix-4 Booth multiplier with 3:2 compressors and Radix-8 Booth multiplier with 4:2 compressors are presented here. The design is structured for m × n multiplication where m and n can reach up to 126 bits. Carry Lookahead Adder is used as the final adder to enhance the speed of operation. Finally the performance improvement of the proposed multipliers is validated by implementing a higher order FIR filter. The design entry is done in VHDL and simulated using ModelSim SE 6.4 design suite from Mentor Graphics. It is then synthesized and implemented using Xilinx ISE 9.2i targeted towards Spartan 3 FPGA.

Tailoring Tests for Functional Binning of Integrated Circuits

Abstract: In recent years, a number of high level applications have been reported to be tolerant to errors resulting from a sizable fraction of all single stuck-at faults in hardware. Production testing of devices targeted towards such applications calls for a test vector set that is tailored to maximize the coverage of faults that lead to functionally malignant errors while minimizing the coverage of faults that produce functionally benign errors. Given a partitioning of the fault set as benign and malignant, and a complete test vector set that covers all faults, in this paper, we formulate an integer linear programming (ILP) problem to find an optimal test vector set that ensures 100% coverage of malignant faults and minimizes coverage of benign faults.We also propose a test strategy based on selectively masking appropriate outputs of the circuit to partition the circuits at production test into three bins - malignant, benign, and fault-free. As a case study, we demonstrate the proposed ILP based test optimization and functional binning on three adder circuits: 16-bit ripple carry adder, 16-bit carry lookahead adder, and 16-bit carry select adder. We find that the proposed ILP based optimization gives a reduction of about 90% in fault coverage of benign faults while ensuring 100% coverage of malignant faults. This typically translates to an (early manufacturing) yield improvement of over 20% over what would have been the yield if both malignant and benign faults are targeted without distinction by the test vectorset.

A Reconfigurable Parallel Prefix Ling Adder with modified Enhanced Flagged Binary logic

Abstract: This paper presents a Reconfigurable Parallel Prefix Ling Adder. The proposed design can be partitioned to perform as one 16 bit, two 8 bit and four 4 bit adders. We also propose a new architecture for Enhanced Flagged Binary Adder (EFBA) designs which reduces the delay of operation considerably. The new adders are, therefore, modifications of conventional Reconfigurable Carry Lookahead Adder (CLA) — EFBA arrangements. We estimate a reduction of 6.8% in the delay in the critical path with respect to traditional implementation of CLA-EFBA logic. The proposed architectures are compared with the previous architectures in literature and are shown to perform better.

18×18-bit radix-4 multiplier embedded in FPGA and based on modified Booth algorithm

Abstract: A multiplier embedded in FPGA was designed.It can perform 18×18-bit signed number or 17×17-bit unsigned number multiplying operation,and is based on modified Booth algorithm.In order to improve the speed of the multiplier,a new structure of Booth encoder and partial product was proposed,and 9-2 compressed tree and carry lookahead adder(CLA) were optimized.TSMC 0.18 μm CMOS technique is adopted in this multiplier.Its critical path delay is 3.46 ns.

High Speed 16×16-bit Low-Latency Pipelined Booth Multiplier

Abstract: This paper presents a high-speed 16×16-bit CMOS pipelined booth multiplier. Actually in an n-bit modified Booth multiplier, because of the last sign bit, n/2 +1 partial product rows are generated rather than n/2. The extra row not only increases the delay and power consumption of Wallace tree, but also it leads to irregularity and complexity of Wallace tree designing. In this multiplier the last sign bit is removed by using a simple high-speed approach. This causes 4% reduction in power consumption and 5.2% reduction in transistor count. Also by using new partial product generation and booth encoder circuits and a novel adder, speed of pipelined multipliers is improved. By these new architectures, final adder performs 25 bit addition in only two cycles with high speed (1.6 GHz). Due to lower number of cycles (5 clock cycles), delay of the overall circuit is only 3.1ns and besides power consumption is decreased so that at a data rate of 1 GHz and under the supply voltage of 3.3V, power consumption is 169mW. This multiplier is implemented in TSMC 0.35µm CMOS technology.