Showing papers on "Clock domain crossing published in 1977"

Circuitry for reducing power dissipation in equipment which operates in synchronism with clock pulses

Abstract: A minimum number of clock pulses required for keeping an electronic component in a waiting condition or state are intermittently applied to the electronic component, thereby minimizing the heat dissipation thereof. A control circuit, utilized in the invention, provides an output signal which permits continuous clock signals to be applied, for example, to memory chips, during read and write periods, but such control circuit reduces the number of clock signals applied to the memory chips during periods when the read and write processes are not required.

Clock system having a dynamically selectable clock period

Abstract: A clock system for providing rectangular wave forms or wave trains, with each wave train having a selectable predetermined clock cycle period. A rectangular wave train is generated by a generator comprising a delay line coupled to an INVERTER. By using a second delay line to delay the rectangular wave by a selectable predetermined delay period, a control signal is formed which when fed into the generator produces a second rectangular wave train with a clock cycle period equal to that of the rectangular wave clock cycle period plus the period of the second predetermined delay. The addition of a synchronization circuit permits the clock cycle period to be dynamically selected during a clock cycle. This provides a rectangular train with the period of each clock cycle being any of the predetermined clock cycle periods independent of the clock cycle period of preceding or succeeding clock cycles.

Asynchronous validity checking system and method for monitoring clock signals on separate electrical conductors

Abstract: An asynchronous validity checking system and method is disclosed for monitoring a plurality of clock signals carried on separate electrical conductors to assure continuing transitions of each clock signal. A master clock is utilized to produce a plurality of phase-related clock signals on the separate electrical conductors, and the transitions of the clock signals are sensed on each electrical conductor adjacent to the distribution point to a controlled unit to assure that all clock signals are continuously operational. The validity checking system includes a locking synchronizer having a plurality of flip-flops each of which receives a different one of the clock signals and a timing signal from a timing oscillator that is independent of, and asynchronous with respect to, the clock signals from the master oscillator with the clock signals being locked into the flip-flops on the rising leading edges of the pulses of the timing signal. A sequence and presence checking unit receives the output signals from the flip-flops and produces reset pulses which are coupled to digital counters incremented by the falling trailing edges of counter clock pulses that are frequency related to the timing signal pulses coupled to the locking synchronizer. As long as transitions of the clock signals are sensed on each of the electrical conductors to reset the counters within a predetermined period of time, no fault indication is produced. If a transition is not sensed, however, the counters are not reset within the predetermined period of time and a fault indication is produced that is indicative of a defect in a clock signal. Upon sensing of the failure of a transition of a clock signal, a fault indication is produced which may be utilized to automatically effectively stop the clock, selectively switch power off, or switch the master clock from a controlled unit, such as a magnetic recording device, to prevent damage and/or information loss.

Output buffer synchronizing circuit having selectively variable delay means

Abstract: Output buffer synchronizing circuit having selectively variable delay means to compensate for different output delays of a processor when the latter operates in different modes. A buffer clock is not only synchronized with the processor clock but also switched in frequency only when in proper phase therewith by delaying a reference signal by kT R /N, where N is the ratio of the reference period to the processor clock period, T R is the reference period, and k is a selectable integer such that 0 ≦ k - N≦1.

System and method for clocking data between a remote unit and a local unit

Abstract: An automatic clock phase adjustment circuit is incorporated in a local unit of a data clocking system. The local unit also includes a clock pulse generator and a local data storage device. The system also includes a remote unit having a remote data storage device. The automatic clock phase adjustment circuit receives clock pulses from the generator and produces output clock pulses having first and second half periods interconnected by a clocking transition which when applied to the remote storage device causes clocking out of data to the local storage device. The circuit also produces a sampling pulse during each of the first and second half periods of the output clock pulses and is operable to detect in which particular one of the half periods a positive transition in the incoming data has occurred during the interval of a sampling pulse in that half period. This permits the circuit to produce local or input clock pulses for clocking in the incoming data at the local storage device during the other of the half periods so that the clocking edges of the input clock pulses will not coincide with any of the positive transitions of the incoming data when applied to the local storage device. As a result, reliable storage of the incoming data is guaranteed to occur at the local storage device at times when the data is stable.

Clock generator for video signal processing

Abstract: A clock generator is provided which demodulates the burst subcarrier portion of a video signal containing time base errors. The demodulation is with respect to an external subcarrier reference signal so that the demodulator output represents an accurate vector summation of the instantaneous phase and amplitude difference of the incoming video signal relative to the external reference. The demodulator output is utilized to remodulate the external reference signal to provide a rephased subcarrier reference signal which is frequency multiplied and waveshaped to produce a clock signal which is synchronized to the incoming video signal.

Clock pulse signal generator having an automatic frequency control circuit

Abstract: A clock pulse generator which has the frequency of its output automatically controlled by comparison of the generated clock pulses with an external reference signal comprises an input for receiving the reference signal, a voltage controlled oscillator for generating the clock pulses, a counter for frequency-dividing the clock pulses to obtain a comparing signal having substantially the same frequency as the external reference signal, a phase comparator for comparing the phase of the comparing signal with the phase of the external reference signal and providing the control voltage for the oscillator in response to a detected phase difference therebetween, and an inhibiting circuit for inhibiting the control voltage whenever the phase of the external reference signal is outside a predetermined range with respect to the comparing signal.

Miller-encoded message decoder

Abstract: A device for decoding a Miller-encoded message in the form of binary data at a clock frequency F. The decoder comprises: a transition detector which provides a very short pulse at each transition in the encoded message; first means controlled by a local clock at frequency F to pass only those short pulses which have the same phase; second means for stretching the short pulses passed by the first means to a duration of (1/2F); a local clock phase lock loop acting on a voltage-controlled oscillator of the local clock and responsive to the output signal of the second means; and a flip-flop to sample the output of the second means under the control of the local clock.

Phase lock loop data timing recovery circuit

Abstract: A phase locked loop including a voltage-controlled oscillator and a divider is used to derive a clock timing signal from a received data stream having a given bit transmission rate. The divider may be programmable so that the circuit can derive a clock from a data stream having any one of a plurality of integrally-related bit rates. A second phase locked loop (having a second programmable divider) is inserted in the feedback path to permit clock recovery from data streams having fractionally-related bit rates.

Bidirectional data communication system

Abstract: A bidirectional data communications system having many remote terminals operating with a central unit includes means at each terminal for reproducing a clock from the incoming data. Upstream data from the terminals to the central unit is transmitted at the same frequency as the incoming data using the reproduced clock from the downstream transmission. At the central unit, the incoming data from each terminal is of arbitrary phase, but must be extracted without delay from the upstream transmission for data processing purposes. A clock signal substantially resynchronized with the data stream is provided by detecting the initial presence of data, and timing the frequency division of a higher frequency original clock so that the phase and frequency of the data match the clock requirements at the central unit.

Stabilized delay line oscillator

Abstract: A device and technique for providing stability to a coherent delay line clock. A voltage controllable delay is combined with the lumped delay line of a coherent delay line clock to enable the control of the period of the clock. The voltage controllable delay is obtained by comparing the clock count during a predetermined time period against a fixed number N to obtain a difference count. The difference count is then integrated to form a bias voltage for control of the additional delay. The delay line period will then be a ratio of the predetermined period to the fixed number N, which number may be digitally modified to provide a source of variable frequency.

Combined timekeeper and calculator with low power consumption features

Abstract: A combined timekeeper and calculator implemented on an LSI semiconductor chip includes a generator stage for generating basic clock signals and system clock signals which are obtainable by modifying the basic clock signals, and a processor stage responsive to the supply of the system clock signals for performing the operations required for the timekeeper mode and calculator mode. The basic clock signals also are modified to create second signals useful in the timekeeper mode. The generator to supply the processor unit with the system clock signals while the second signal is being generated. Upon completing the operations by the processor unit, a clock control circuit prevents the processor unit from being supplied with the system clock signals.

Remote control system for selective load switching, specifically for automotive vehicles

Abstract: A central station is connected to a ring bus system to which a number of separately addressable loads are connected through specific load receivers. The central station has a switching system by operation of selected switches of which, specific loads can be addressed. The ring bus system has a power line or bus, a clock line or bus, and a control line or bus. The clock line provides clock pulses during a selection cycle, and upon coincidence of a clock pulse with a pulse on the control bus, a specific load associated with a predetermined numbered pulse on the clock line can be addressed by sensing coincidence of the pulse on the control line and on the clock line. To separate selection cycles, a control signal is transmitted which may form a pause of clock pulses on the clock line. This control signal, in accordance with the invention, is represented by a series of pulses transmitted on a line other than the clock line, for example on the control bus. It is generated by a pulse generator in the central station to supply a predetermined number of such pulses on the control line only. The receivers have suitable receiver counters which respond to these pulses. Logic circuitry can distinguish between the selection pulses, which will have coincidence on the clock bus and on the control bus, and clock pulses which will appear only on the clock bus. The synchronization pulses are of a predetermined number which will appear only on the control bus so that the respective function synchronization counters in the central station and in the receiver will be synchronized anew for each selection cycle by digital evaluation of the function synchronization pulses.

Automatically regulated quartz clock - is synchronised with received time signal via slave clock periodically used to correct time registers

Abstract: The quartz clock is combined with a slave clock, receiving a master time signal, which periodically corrects the contents of the time registers coupled to the display for the quartz clock. The slave clock may be coupled in circuits for correction of the quartz clock for a short period upon the display reaching a predetermined time indication. Pref. an alarm is actuated if the time information provided by the quartz clock and the slave clock differs by more than a given amount. This alarm signal may be provided by causing the seconds indication to operate at twice its normal rate.

Multi-level encoding system

Abstract: An encoder providing on a single terminal of a circuit package a composite serial data stream containing both stored data bits of a multistage binary memory and a clock signal needed for decoding the data. A parallel to serial converter serially shifts the stored binary data bits to an output thereof in response to clock pulses of an internal clock, and a logic circuit responsive to both the internal clock and the serial binary data from the converter generates first, second and third signals of amplitudes discernibly different from one another respectively in response to 1-state data bits, 0-state data bits and the termination of clock pulses. Two fixed inputs to the converter respectively provide a 1-state start bit at the beginning of the set of data bits and a 0-state stop bit at the end of the set of data bits for purposes of decoding. An amplitude discriminating decoder uses the periodic third signals and the start and stop bits to decode the serial data.

Variable function generator

Abstract: A fully digitalized function-of-time generator suitable for use as a tone envelope generator in a digital electronic musical instrument, comprising: a clock pulse generator for generating a clock pulse at a selectable rate; a gate enabled at each arrival of the clock pulse; a single-stage binary shift register for successively shifting out its contents as a digital word representing the instantaneous values of a desired function of time synchronously with the clock pulse; a digital subtractor; a digital multiplier; and a digital adder, all of these members being interconnected to each other to be operative so that the output of the register is subtracted from a first set value representing a digital word, the resulting difference being multiplied by a second set value representing a digital word, the resulting product being added to the output of the register via the gate, so that the resulting sum is loaded into the register. Thus, the contents of the register approaches progressively toward the first set value, and finally becomes in agreement therewith. Thus, this musical instrument can produce a musical tone rich in expression and imparted with desired tone envelope characteristic, by appropriate choice of one or more of the first and the second values and the rate of the clock pulse.

Clock driven voltage comparator employing master-slave configuration

Abstract: A pair of clock driven voltage comparators are arranged in a master-slave configuration so that voltage comparisons are made only on a clock edge and the output is held valid over the entire clock period. Each comparator stage includes a latch to lock the comparator output in the logical state it was in when the latch was enabled.

Integrated circuit having one-input terminal with selectively varying input levels

Abstract: An integrated circuit includes an input terminal to which a "1," "float" and "0" level input signals are selectively supplied; a clock pulse generator for generating a second clock pulse during the high level period of a first clock pulse and a third clock pulse during the low level period of the first clock pulse, and first and second latch circuits operated in response to the second and third clock pulses, respectively, of the clock pulse generator. The input terminal is connected through a resistor to the output of the first clock pulse. The input terminal is also connected to the inputs of the first and second latch circuits. The integrated circuit generates three kinds of outputs whose logical states correspond to different levels of three input signals, respectively, which are selectively supplied to said input terminal.

Exposure time control

Abstract: An improved exposure time control for a photographic printer includes a digital processor such as a microprocessor. The digital processor receives input signals such as signals from large area transmission density (LATD) sensors, from density or color sensors, and from an operator control panel. Based upon the input signals, the digital processor derives a digital count and a clock control signal for each color channel. The exposure of each color channel is controlled as a function of the time required to change the corresponding digital count from its initial value to a predetermined final value. The changing of the digital count for each channel is caused by the digital processor in response to clock or interrupt signals from variable clocks controlled by the clock control signals. The rates at which the interrupt signals are generated are controlled by the clock control signals.

Digital phase lock loop circuit and method

Abstract: A digital phase lock loop circuit and method wherein the phase and the frequency of an output clock pulse of the circuit are made to instantaneously coincide with the phase and the frequency of an input clock pulse of the circuit. The digital phase lock loop circuit includes a fixed frequency generator circuit, an output frequency divider to which a standard clock pulse from the fixed frequency generator circuit is supplied via an inhibit gate, an output clock pulse frequency divider which divides the frequency of the output clock pulse from the output frequency divider, a phase comparator to which the input clock pulse and the divided clock pulse from the output clock pulse frequency divider are provided and an inhibit pulse generator to which the output of the phase comparator is supplied, so as to provide an inhibit pulse from the inhibit pulse generator to the inhibit gate. Further, according to the present invention, a clear pulse generator is provided for the purpose of forming a clear pulse which clears the contents of the output frequency divider and the output clock frequency divider. Such clear pulse is generated based on the condition that the time difference between a first occurrence (the frequency division of the output frequency divider being actuated by the standard clock pulse after the output frequency divider, and the output clock frequency divider being cleared by the clear pulse) and a second occurrence (the frequency division of the input frequency divider being actuated by the input clock pulse) is smaller than a predetermined period of the standard clock pulse.

High resolution auto-zero circuit for analog-to-digital converter

Abstract: An analog-to-digital converter includes an integrator which includes an amplifier having an offset voltage. A counter is responsive to a counter clock signal for counting during the duration of a first integration and transferring its count at the end of the first integration to a storage circuit. The counter is then reset. It then counts during the duration of a second integration. Coincidence circuitry is provided which causes the counter to be reset during the second integration when its count matches the count stored in the storage circuit. The counter then continues counting until the end of the second integration. The uncertainty associated with the count stored in the counter at the end of the second integration is improved by provision of a circuit responsive to the comparison signal and first and second clock signals for producing the counter clock signal. The counter clock signal is produced such that it is in phase with the first clock signal if the comparison signal at the end of the first integration occurred before the beginning of a subsequent pulse of the second clock signal. Otherwise, the third clock signal is delayed so that it is temporarily in phase with the second clock signal.

Linear digital phase lock loop

Abstract: A linear digital phase locked-loop generates a recovered clock which is synchronized with level transitions in the data signal being tracted Internally generated clock pulses are cyclically counted to generate a binary ramp signal This ramp signal is added to another digital signal whose value depends upon the phase and frequency departure of the data signal from the recovered clock A first order linear accumulator supplies a modified summation signal upon transistions in the data signal and the recovered clock is adjusted to fall in sync with the data A second order loop may be selectively employed for phase and frequency tracking The second order loop includes a further linear accumulator which supplies a digital signal to be combined with the binary ramp signal to adjust the recovered clock frequency until the first and second order loops are stablished, at which time the clock is synchronized with the data As the first and second order loops stabilize, the composite behavior is linear and may be described by classical second order servo-control loop equations This allows for linear analysis of systems using this bit synchronizer as a system component

Memory scanning radio receiver with separate channel data selection

Abstract: A radio receiver having RF, frequency converter, demodulator and audio stages, in which the frequency converter stage is connected to a local oscillator composed of a phase locked loop. The radio receiver includes a variable frequency divider inserted into the phase locked loop, a memory circuit for variably controlling the frequency dividing ratio of the frequency divider in accordance with a signal to be received, a scanning counter for supplying a read-out control signal to the memory circuit, a clock signal source for generating a clock signal, a counter control circuit for controlling supply and supply-terminating of the clock signal fed to the scanning counter, a level detecting circuit for detecting if a signal supplied to the RF stage has a level higher than a predetermined level, a switching circuit for switching a received channel, and a circuit for cutting off the clock signal fed to the scanning counter when outputs of the switching circuit and level detecting circuit are fed thereto.

Tone signal detector

Abstract: A digital tone signal detector having N-path filters eliminates the need for a variable-frequency active filter and makes possible the use of integrated circuits in paging receivers, transceivers, mobile radio equipment and so forth. The tone signal detector comprises a clock pulse generator, an N-path filter (where N is an integer equal to or greater than 2), a low-pass filter, a wave shaping circuit, a gate circuit, a counter and detection circuitry. The clock pulse generator generates clock pulses of a predetermined frequency Fc equal to N times the frequency fo of tone signals. The N-path filter samples and selects the tone signal of the frequency fo according to the output of the clock pulse generator. The low-pass filter converts the sampled tone signal including the clock frequency component into a form close to sine wave to eliminate the clock frequency component. The wave shaping circuit shapes the output of the low-pass filter to produce pulses, and the gate circuit passes the clock pulses in accordance with the output of the wave shaping circuit. The counter is connected to the output of said gate circuit to count the number of the output pulses of the gate circuit. The detection circuitry is connected to the counter to detect whether or not the received tone signals are the designated tone signals by the count accumulated by the counter in a prescribed period of time.

Method for storing a binary signal in a high speed flip flop memory having controlled minimum changeover time and apparatus therefor

Abstract: A method for storing a binary signal in a high speed flip-flop memory. The apparatus includes a clock signal selecting device connected to control a pair of memory elements in cascade. Data is introduced into the first memory element under the control of a first control signal from the clock signal selecting device and is transferred to the second memory element under the control of a second control signal from the clock signal selecting device. A single output of a clock pulse generator is applied via parallel lines, one of which includes a delay element, to a logic gate to provide spaced time pulses which are applied to the clock signal selecting device. The clock signal selecting device includes a pair of two input AND gates, each of which are connected to receive at one input the spaced time pulses and at the second input a clock signal selecting signal derived from the output of a JK flip-flop having its sync input connected to receive the spaced time pulses.

Digital clock for motor vehicles

Abstract: A digital display clock for motor vehicles having a clock driving section for generating time signals continuously regardless of the on or off state of an ignition switch and a digital time display section consisting of an electric current consuming type luminescent element for displaying prescribed digital time. The display action of the digital time display section is controlled by both a main switch means and an auxiliary switch means connected in parallel with each other.

Electronic clock radio having nap/sleep feature

Abstract: An electronic clock radio using a clock integrated circuit and a radio integrated circuit. A first energizing potential when applied to the NAP/SLEEP input connection of the clock circuit, causes the clock circuit to switch from a first electric state to a second electric state. After a selected interval of time, not greater than 60 minutes, the clock circuit switches from the second electric state to the first electric state. The radio, normally in an OFF state is placed in an ON state only upon receiving a second energizing potential applied to its input connection. A control circuit, having a manually operable switch with NAP and SLEEP positions and being responsive to the electric states of the clock circuit, connects this second energizing potential to the radio input only when: (i) the manually operable switch is in the NAP position and the clock circuit is the first electric state, or (ii) the manually operable switch is in the SLEEP position and the clock circuit is in the second electric state.

Clock circuit for use in pulse-echo ultrasonic defect testing

Abstract: A clock circuit comprising a synchronizable voltage controlled oscillator in combination with a programmable address means, which address means is adjusted commensurate with the acoustic velocity of the workpiece, provides clock pulses from the oscillator having a stable and accurate acoustic velocity dependent frequency. An entrant surface responsive electrical signal responsive to an ultrasonic search signal entering the workpiece is also provided to the clock circuit for assuring that the clock pulses are synchronized with the receipt of the electrical signal.

Log in-out system for logic apparatus

Abstract: A plurality of logic circuits having log in-out functions are connected in sequence. A clock distribution circuit is connected to each sequential logic circuit via a corresponding one of a plurality of bidirectional lines. A mode designation signal is supplied in common to each sequential logic circuit and the clock distribution circuit. A sequential logic circuit selection signal, which selects one of the sequential logic circuits, is supplied to the clock distribution circuit. A clock signal is supplied from the clock distribution circuit to each sequential logic circuit via the bidirectional lines in the clock mode. Log in data is supplied from the clock distribution circuit to the sequential logic circuit via a specific bidirectional line in accordance with the sequential logic circuit selection signal in the log in mode. Log out data is supplied to the clock distribution circuit from the sequential logic circuit in the log out mode via a specific bidirectional line in accordance with the sequential logic circuit selection signal.

Electronic phase detector circuit

Abstract: An electronic phase detector circuit includes a variable period sawtooth generator. The sawtooth generator receives digital reference clock signals and in response thereto generates sawtooth-shaped signals having the same period as said reference clock signals. A sample and hold circuit samples the sawtooth-shaped signals in response to one logical state of a sampling clock. A voltage controlled oscillator is coupled to the output of the sample and hold circuit and oscillates at a frequency proportional to the magnitude of the held sample.