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Patent

Clock driven voltage comparator employing master-slave configuration

TLDR
In this paper, a pair of clock driven voltage comparators are arranged in a master-slave configuration so that voltage comparisons are made only on a clock edge and the output is held valid over the entire clock period.
Abstract
A pair of clock driven voltage comparators are arranged in a master-slave configuration so that voltage comparisons are made only on a clock edge and the output is held valid over the entire clock period. Each comparator stage includes a latch to lock the comparator output in the logical state it was in when the latch was enabled.

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Citations
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Patent

High speed comparator circuit with input-offset compensation function

TL;DR: In this article, a comparator circuit consisting of a differential amplifier provided with an input offset voltage compensating circuit which stores the offset voltage and derives an offset-free output signal from the amplifier in response to first and second states of a first control signal.
Patent

Metastable-immune flip-flop arrangement

TL;DR: A D-type flip-flop arrangement includes first and second latches (30, 46) and circuitry interposed between the latches blocks any metastable condition that may occur in the first latch from propagating into the second latch as mentioned in this paper.
Patent

High speed input receiver/latch

TL;DR: In this paper, a high-speed receiver/latch is implemented by incorporating a differential amplifier/comparator directly into the feedback loop of a latch function, which is capable of extremely high speed operation by virtue of very small setup time and small propagation delay.
Patent

Pseudo-dynamic differential flip-flop

TL;DR: In this paper, a differential flip-flop using only one current source, as opposed to the two typically required by its conventional counterpart, saving fifty percent of the total power requirement.
Patent

Sense circuit with presetting means

TL;DR: A circuit whose output is asymmetrical whereby the circuit makes a transition from a first state to a second state more slowly than from the second state to the first state is considered in this article.
References
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Patent

Bistable multivibrator circuit

L Mesa, +1 more
TL;DR: In this article, a bistable multivibrator circuit which is readily adaptable to monolithic integrated circuit technology combines the master and slave portions and utilizes split current sources to reduce the components needed to provide a master/slave circuit operation.
Patent

Zero crossing detecting circuit

B Garrett
TL;DR: In this article, a zero crossing detecting circuit is provided for detecting each zero crossing of a data signal without interference from noise during a data detecting or decoding operation, and a bistable latch is applied to logic circuitry to prevent the latch from changing state in response to a succession of immediately following noise-produced zero crossings.