Showing papers on "Clock generator published in 1981"

Weighted erasure codec for the (24, 12) extended Golay code

Abstract: A codec consists of an encoder and decoder. The encoder provides 12 information bits, 11 parity bits generated according to the polynomial for the (23, 12) Golay code, and an overall parity bit to a transmitter at selected transmit times to form a 24-bit block of data. The decoder is separated into two independent list decoders, a comparator, and common clock generator and output buffers. Each list decoder is divided into a syndrome generator and an overall parity check generator, a syndrome error pattern table, an input buffer, error correction logic, and four-error detection logic. The error pattern table includes a pair of read only memories storing the most likely 12-bit error patterns at each ROM address corresponding to each syndrome. An additional 4-bit output is used to indicate the number of errors in the associated error pattern. The comparator compares the number of errors detected in the two independent decoders and chooses the decoder having the fewer number of errors to provide the corrected data.

System clock generator in integrated circuit

Abstract: A system clock generator for use in a CMOS LSI chip includes a clock control signal generator for developing a control signal in response to a clock generating instruction or inhibition instruction; and a clock generator supplied with the output of an oscillator for developing a basic clock of a desired waveform for supply to the system, wherein the basic clock is developed or inhibited when the control signal is supplied from the clock control signal generator.

Clock generator circuit

Abstract: A clock generator circuit for generating two pairs of clock signals (φ2, φ 2 - φ1, φ 1) comprises a NAND circuit (51) and a NOR circuit (52) cross-coupled to each other and each having an input for receiving a reference clock signal (φ0). A first inverter (53) is provided between the output of the NAND cicuit (51) and the other input of the NOR circuit (52), and a second inverter (54) is provided between the output of the NOR circuit (52) and the other input of the NAND circuit (51). A pair of clock signals (φ 2, φ2) are generated from the NAND circuit (51) and the first inverter (53), while the other pair of clock signals (φ1, φ 1) are generated from the NOR circuit (52) and the second inverter (54). Unwanted overlap of such clock signals can thereby be avoided.

Interface for data communication systems using serial biphase data transmissions

Abstract: An interface for biphase data communication systems utilizing serial transmissions between a central control unit and a peripheral device. A ROM-latch network serving as a sequencer is utilized as a bi-directional biphase serial/TTL parallel translator. In the receiver mode the ROM-latch will step through a specific operational sequence for detecting an appropriate header and controlling a TTL parallel translation of the serial biphase data. In the transmitter mode the ROM-latch is used to reconstruct the header sequence prior to retranslating and transmitting the TTL parallel data in serial biphase format. A receiver clock generator circuit is provided for generating clock pulses for the ROM-latch in synchronism with the incoming biphase transmissions. A transmitter level converter defines the waveforms for the biphase data transmitted from the interface and is designed to provide a predistortion pulse at each voltage level transition.

Car height adjusting unit

Abstract: PURPOSE:To allow a driver to take the most suitable action quickly by detecting an irregularity when it occurs so as to indicate the occurrence of the irregularity. CONSTITUTION:When a car height raising control or a car height lowering control is performed, the output of an NOR gate NOR2 is turned to (H) and the output of an OR gate OR4 is truned to (H), then a transistor Tr3 is turned on and a lamp LP is lighted. If at least one of irregularity detection circuits detects an irregularity, the output of an OR gate OR1 is turned to (H) and an AND gate AND6 is opened, then frequency divided clock pulses from a clock generator are applied to the base of the transistor Tr3 through the AND gate AND6 and OR gate OR4. Therefore, the transistor Tr3 is turned on and off, thus indicating the occurrence of an irregularity.

Clock synchronization signal generating circuit

Abstract: A clock synchronization signal generating circuit includes a clock synchronizing circuit having a scale variable counter for counting a source clock signal from a source clock generator and a control circuit for controlling the scale of counter responsive to the phase difference between an input clock signal supplied from a digital operation system and an output signal from the scale variable counter, and a clock circuit including a counter for counting in n-scale mode a source clock signal from the source clock generator. The scale variable counter is selectively set to (n-1)-, n- or (n+1)-scale mode responsive to the control signal from the control circuit to generate an output signal which is clock-synchronized with the input clock signal.

Color-television receiver with at least one digital integrated circuit for processing the composite color signal

Abstract: The color television receiver includes a square-wave clock generator used as a chrominance subcarrier oscillator generating at least four clock signals, the first of which has a frequency four times the chrominance subcarrier frequency, and the second to fourth of which have a frequency equal to the chrominance subcarrier frequency, the first and second clock signals having a mark/space ratio of 1:1; a stage providing a digital chrominance signal, a first digital circuit having as one input signal the digital chrominance signal, and as another input signal the digital chroma control signal to provide a digital amplitude control of the received chrominance subcarrier wave; and a second digital circuit to provide digital PAL identification and color killer action and, if necessary, digital noise-dependent color killer action.

Clock control for digital computer

Abstract: A master clock for a microprogrammed digital computer generates output pulses whose separation in time can be varied in response to each microinstruction or to a process-related signal. The output pulses are formed from basic time units from a clock generator which are combined, in digital logic circuitry, to form a minimum time interval and supplemented, under command, with the necessary additional time units to delay the next output pulse by the required amount of time.

MOS Capacitive bootstrapping trigger circuit for a clock generator

Abstract: A trigger circuit is described for use in an MOS clock generator. The clock generator is the type which uses a conventional double bootstrapping circuit coupled to a control transistor to develop a high level clock output signal. The trigger circuit preconditions the control transistor to facilitate proper bootstrapping operation. Included in the trigger circuit is a plurality of interconnected transistors which respond to a pre-charge signal and then a warmup signal for turning the control transistor off and then for establishing selected potentials at the electrodes of the control transistor to precondition it for bootstrapping. In response to a subsequent trigger signal, the trigger circuit enables the control transistor for developing a high level clock output signal.

Clock circuit for generating non-overlapping pulses

Abstract: A clock generator for producing a two phase output comprises a bistable circuit having two stages. The output of each stage is cross coupled to the input of the other and each cross coupling path includes a high-resistance transfer gate. Each transfer gate forms part of an RC delay element which is so arranged that at a transition of clock signals the output of one of the stages completes its transition substantially at the same time as the output of the other stage begins its transition. This results in non-overlapping outputs from the generator.

Image sensor checking machine

Abstract: PURPOSE:To improve the quality of the image sensor to perform the checking work efficiently, by counting clocks with the bit counter and by detecting the input voltage outside the upper and lower limits of the slice voltage by the checker to check the image sensor automatically in a short time. CONSTITUTION:Outputs of respective bits of image sensor 2 which received the initial light quantity of light source part 14 are transmitted successively by prescribed clocks from clock generator 10. The output voltage reference value due to the prescribed light quantity of sensor 2 is denoted as V0, and the output of sensor 2 is amplified in 11 by amplification factor A; and when the output of the amplifier becomes V1, it is detected by sensor output reference value setting detector 12 to fix the light quantity, and the initial reset signal is transmitted to the bit counter. Counter 17 counts clocks from clock generator 10, and checkers 15A and 15B detect the input voltage outside upper and lower slice voltages and display it. As a result, sensor 2 is checked automatically in a short time to improve the quality of sensor 2 and make the check work efficient.

System for regenerating a data word on a communications ring

Abstract: A system for regenerating an n-bit data word on a token mediated communications ring includes a decoder for receiving the data signal from the ring and deriving the n-bit data word and an associated clock signal from the received data signal. A re-transmit clock generator generates a transmit clock signal incorporating the i th through the n th cycles from the derived clock signal, followed by i cycles at the nominal system clock rate. A delay network delays the derived data word by a period approximately equal to the period of the nominal system clock. An encoding network regenerates the n-bit data word for re-transmission on the ring by encoding the delayed derived data word with the transmit clock signal.

Space diversity receiver with means for combining signals from the two channels

Abstract: A space diversity receiver with a combiner in which the useful signals of two space diversity receiver branches are connected together with a summing amplifier in the IF frequency band, and wherein an electronically controlled phase corrector P is mounted in one of the receiver branches and in which a phase monitoring circuit provides an output signal to control the phase corrector and is connected at the output of the electronic phase corrector between the two receiving branches. The space diversity receiver is constructed in the simplest possible manner with the lowest possible electrical interference and provides that the phase monitoring circuit consists of a phase discriminator D1 to which the signal from one reception branch is supplied through an automatically gain control amplifier RV2 without phase shift and the signal from the other receiving branch is supplied with an identical automatically gain controlled amplifier RV1 and through a 90-degree phase shifter. The output signal of the phase discriminator D1 is supplied to a comparator K0 and to a square law transfer circuit QS and depending on its absolute value determines the clock frequency of a clock generator T that drives a forward/backward counter Z. The respective position of the forward/backward counter Z is converted with a memory SP so as to control the phase corrector P which can be set in a step-by-step manner.

Multi-frequency clock generator with error-free frequency switching

Abstract: A system clock generator includes circuitry for error-free switching of clock frequency. Frequency switching is necessary, for example, when the main power supply fails and to conserve standby battery energy the system is operated at a low clock frequency. Conversely, when the main power source is restored, system clock frequency must be returned to normal. The clock generator and switching circuitry comprise two bistable switch circuits and an RC (resistance-capacitance) oscillator made up of a NAND gate, an inverter, and an RC network. One of the bistable switch circuits includes means for detecting the presence of signals indicating the existence of a condition requiring frequency switchover.

High accuracy redundant clock signal supplying circuit - uses majority decision circuits and several regulated clock generators

Abstract: The circuit has a number of similar clock generators (1..4), each with a phase-locked loop having a voltage-controlled oscillator, its control input connected via a low pass filter to a phase comparator, comparing the oscillator signal with a reference clock signal. Each clock generator (1..4) has a majority decision circuit coupled to the incorporated oscillator and to the oscillators of the other clock generators and providing the reference clock signal for the phase comparator. The clock signals of the oscillators of all the clock generators (1..4) are supplied to an external majority decision circuit providing the output clock signal.

Memory conservation method in a programmable ROM sync generator system

Abstract: A television synchronization generator has a clock generator driving a ROM. The ROM has stored in it the required sync signals. In order to conserve the ROM size, the ROM is addressed by a counter except during portions of the sync signals when the amplitude remains a constant. During these portions the counter continues to count.

Improvements in or relating to wafer scale integrated circuits

Abstract: A wafer scale integrated circuit wherein a plurality of data processing cells (12), such as memory cells, all on a single wafer (10) are connectable into a chain (18) starting at a port (14) for passing data away from the port (16) via a serial connection of forward registers (38) and back towards the port (14) via a serial connection of reverse registers (40), has a reduced risk of any individual, otherwise perfect cell (12) being non-functional as a result of a failure elsewhere on the wafer (10) of an associated Global line by achieving a reduction in the number of Global lines required by providing a data shift controlling master clock signal which is transferred between the cells (12) in parallel with the data and is used to operate a multiple clock generator (46) in each cell.

Character pitch processing system

Abstract: PURPOSE:To enable high-speed processing and to simplify the processor, by changing the dot interval with the adjustment of the number of dots and making unnecessary a plurality of clock generators for frequency conversion without adjusting the dot interval. CONSTITUTION:The character pattern of a given bit read in from the character pattern memory 51 is stored in the row buffer in the specified word unit and dot split is made in row unit. Further, among the row dot pattern read out in word unit, the head bit is delivered to the counter 52 and the remaining bits are delivered by switching one of the shift registers 63-a and 63-b. Further, in the switching circuit 56, the AND gate 57 is open by the time when the number of effective bits is delivered to the print section PRT with the control signal 58 from the counter 52, and synchronism is taken to the clock generated at the clock generator 55 to deliver the effective bit from the one of registers 6-a and 6-b.

Controlling device for motor

Abstract: PURPOSE:To enable to digitize the controlling circuit for a motor by a method wherein the clock pulse number in proportion to a revolution speed and the counted number of clock pulse of the frequency higher than said clock pulse number are compared and the ON-OFF ratio of the load controlling element is determined at the time when the above numbers are coincided with. CONSTITUTION:The revolution speed of the motor 1 is detected by a sensor 2 and a counter 6 is inputted through the intermediary of a pulse generator 4 and a delay circuit 5. The counter 6 counts the pulse of a clock generator 7, the frequency of which was divided by a frequency divider 8 between each pulse to be inputted from the delay circuit 5, and the counted value is memorized to a latch circuit 9 for every output pulse of the pulse generator 4. Also, the second counter 11 is operated by the output pulse of the delay circuit 5 and the clock pulse before the frequency is divided is counted. The comparator 10 compares the value of the clutch circuit 9 and the counted value of the counter 11 and the ON-OFF ratio of the transistor 14 to be used for control of power supply is controlled by turning out an output to a flip-flop 13 at the time when said value are coincided with.

Bootstrapped clock driver including delay means

Abstract: A clock generator circuit (10) receives an input signal PPC.0. and generates a delayed clock output signal PC.0.. The circuit (10) is set to an initial condition by a precharge signal PC.0.R prior to a transition of the input signal PPC.0.. A time delay signal is produced at a node (26) by operation of transistors (18, 28). The transition of the input signal PPC.0. produces a bootstrapped voltage at a capacitor (68). The delay signal activates a transistor (80) to couple the bootstrapped voltage to the gate terminal of an output transistor (88). The gate terminal of the output transistor (88) is driven directly from a low voltage state to a boosted high voltage state. This causes the output signal PC.0. to be driven from an initial low voltage state to the power supply voltage V cc without intervening steps. The output transistors (88, 90) of circuit (10) are never activated at the same time, thereby preventing any current spike from being propagated through the circuit (10).

Test unit for semiconductor circuit

Abstract: PURPOSE:To perform the propriety judgement with high reliability, by taking the semiconductor circuit of nondefective goods as the basis of comparison, operating the comparison reference semiconductor circuit and inspected semiconductor circuit under the same condition at the same time, and comparing the timing of output signal. CONSTITUTION:The input ports of the comparison reference semiconductor circuit 11 of nondefective goods and the semicondcutor circuit 13 as inspected body are connected commonly, and the clock signal of a given period is fed to the clock input terminal from the clock generator 14. The signal from the output port of the semiconductor circuits 11, 13 is input to the timing diference detector 17 and the corresponding output is compared for timing at every port. The information detected at the timing difference detector 17 is input to the pulse width detector 18, the controller 15 judges the propriety of inspected semiconductor circuit 13, and the result of judgement is displayed at the display unit assembled at the input and output unit 19.

Method for setting characteristic value of digital signal measuring instrument

Abstract: PURPOSE:To make the setting operation of a set value easy, when an operator has set a characteristic value beyond the range of a characteristic value that is specified beforehand, by automatically setting said limit value of the range as the characteristic value. CONSTITUTION:The output of a data probe 10 is applied to a high speed memory unit 14 and a word recognizer 16 via an input circuit 12. The work recognizer 16 receives logical signals from a terminal 20, and set signals from a bidirectional bus 26. The output of the word recognizer 16 is applied to programmable counter 28 and the output of the counter 28 is applied to the high speed memory unit 14. The memory unit 14, a clock generator 18, the programmable counter 28, a central processing unit 24, a keyboard 22, an ROM32, a CPU RAM 30 and an RAM34 for displaying are connected to the bus 26 respectively. The output of the RAM34 for displaying is displayed on a displayer 36.

Picture signal encoding system

Abstract: PURPOSE:To make it possible to obtain pictures with high quality and less distortion by attaching a movement detecting circuit which detects the movement of picture signals when they are encoded. CONSTITUTION:Color subcarrier SC of an input picture signal is entered into clock generator 33 and, after A/D converting the picture signal with a clock signal whose frequency is 4 times larger than that of SC in A/D converter 34 to perform preparatory encoding, the converted picture signal is entered into prefilter 36. The output of filter 36 is sampled with the 1/2 frequency of the clock signal and the phase of the sampling signal is reversed in every period corresponding to integer times of horizontal scanning period h to transmit the sampling signal. In the receiving side, the input signal is preencoded by interpolating filter 39 to decode the picture signal. Filter 39 compares the sampling picture signal with the picture signal delayed by the integer times of the field period. When picture movement is detected by picture movement detecting circuit 43, switch 49 is connected to the b side, the high component is interpolated with the high component of the picture signal generated before the integer time of period h and the low component is interpolated with the low component of the neighboring picture signal in the same horizontal period.

Signal voltage detecting circuit

Abstract: PURPOSE:To magnify and detect a small voltage difference with low power consumption in a short time, by connecting an MOS transistor, a capacitor, and so on to the prescribed node of a sense amplifier of the MOS dynamic memory to magnify the node potential difference furthermore CONSTITUTION:In case that the signal voltage applied to storage node N1 of the sense amplifier is higher than the voltage applied to node N2, FETs Q1 and Q2 are turned on and off respectively through MOSFETQ5 and so on controlled by clock generating circuit 2 to extend the voltage differece between nodes N1 and N2 Drains of MOSFETs Q6 and Q7 which have sources connected clock generator 5 through capacitors C6 and C7 and so on and have gates connected to clock generator 4 are connected to nodes N1 and N2 respectively; and when FETs Q6 and Q7 are turned on through generator 4 after a high potential is set to source-side contacts N4 and N5 by generator 5, the voltage is added only to node N1, and the voltage difference between nodes N1 and N2 is magnified without DC power consumption to shorten the operation time for detection of a small voltage difference

Speed control system for I.C. engine - monitors speed and fuel consumption to provide optimum control of engine

Abstract: The system utilises sensors to monitor engine speed (R), road speed (V) and fuel consumption (Q). The outputs of fuel sensor and tachometer are fed to a processing stage (3) to determine the instantaneous power. One stage (B) contains a differentiater (4) and an amplifier (5) to provide an indication (6) of effective speed. A further stage (C) contains a voltage quantiser (7), comparator (8), differentiator (9), analogue switch (10) and low pass filter (11) coupled to the coil (12) of the display (13). Fuel consumption is monitored by an analogue to digital converter (14), gate (15) and clock generator (17).

Fuel injection valve driving circuit

Abstract: PURPOSE: To simplify the structure thereof by a method wherein a valve opening current and a holding current are supplied by the time ratio control of a pulse having substantially a constant frequency in the circuit in which the valve opening current and the holding current necessary for maintaining the valve in the opened condition thereof are switched to supply it to the coil of the fuel injection valve. CONSTITUTION: Upon controlling the driving of an injector attached to a throttle chamber, a clock pulse CP is outputted from a clock generator 51 to generate saw tooth wave SW from a saw tooth generator 52. On the other hand, a signal Ve based on the output in accordance with a signal Input inputted into a terminal 20 is outputted from an error amplifier 50, said signal Ve is compared with the signal SW by a comparator 28 and a rectangular wave Vo is generated from the comparator 28 when Ve > SW. A NPN transistor 33 is put On or OFF in accordance with said signal Vo and the current (i) is supplied to a solenoid coil 32, thereby controlling the operation of the injector 33. COPYRIGHT: (C)1983,JPO&Japio

Method for recovering the clock required at the receiving end in a data transmission system and a device for carrying out the method

Abstract: A method is proposed for recovering the clock required at the receiving end in a data transmission system. According to the method, an unsynchronised pulse string corresponding to the clock (ST) at the transmitting end is generated in a clock-generating device (10) at the receiving end. If there is a phase difference between one edge (F1...) of the received binary data (DE) and one edge (F1') of the pulse string, the division ratio of a frequency divider (38) belonging to the clock-generating device is modified in such a way that the existing phase difference is at least partially cancelled. A device for carrying out the method according to the invention essentially comprises a clock generator (41) with a device (40) for frequency division, a logic circuit (31) and two direction detectors (17, 18) with which the direction of the phase difference can be identified and the division ratio of the frequency divider can be modified.

Highly sensitive fault current protection switch responding to any current.

Abstract: The invention relates to a high sensitivity fault current protection switch, responding to any current, which is used particularly in domestic electrical installation technology and consumer networks. The circuit is used for the detection of fault currents of any wave form and for the detection of low resistance connections between the neutral and protective earth lines in the load. In this case, a frequency generated by a clock generator (1) is fed to the secondary winding (3) of a summing current transformer (2), the output of which is connected to a voltage divider (6), by means of which the clock current is made symmetrical. The pulsed signal is passed to a comparator circuit (7, 8) via a winding tapping (4), the pulsed signal being compared with in each case one reference voltage. If the signal is too high and/or too low, the comparators (7) and/or (8) switch on, thus activating the trip relay (12). An RC element (10) with a downstream comparator (11) is used for intercepting parasitic interference peaks.

Method and system for correcting time base errors in broadband signals stored in or transmitted through a plurality of narrow-band channels

Abstract: Time base errors arising during the playback of a broadband signal previously stored in segments in a plurality of narrow-band channels with a first time transformation are corrected. Specifically, these signals are read out in turn from the narrow channels on the tape and applied at a slow rate to a plurality of buffer storages. They are read out from the buffer storages at a relatively fast rate, in sequence, so that the broadband signal is reconstituted. The broadband signal is then demodulated. For time base correction, the horizontal synchronization signals are separated from the reconstituted demodulated signal and their timing is compared to the timing of horizontal reference signals. A pulse is formed whose pulse width is equal to the time interval between occurrence of a horizontal synchronization pulse separated from the demodulated signal and the occurrence of the corresponding reference synchronization signal. The output of the clock generator controlling the readout from the buffer storages is delayed by a time interval equal to the pulse width. Further measures for decreasing residual errors are also specified. The measurement is carried on at the start of each line and after the signal has been reconstituted and demodulated and is thus present in a single channel.

Signal detecting circuit

Abstract: PURPOSE:To simplify and miniaturize a signal detecting circuit greatly by selecting and detecting a signal, which is inputted according to frequency response characteristics of a switched capacitor filter varied in time-division mode, by using the filter and a logic circuit. CONSTITUTION:When an arrival signal from input terminal 1 is inputted to buffer circuit 2, the signal is set to an adequate level by circuit 2 and then applied to switched capacitor filter circuit 3. A clock operating this circuit 3 is supplied from clock generator 9 and according to its clock frequency, desired filter characteristics of filter 3 are varied in time-division mode to apply the output of this filter 3 to detecting circuit 4, thereby obtaining the output of only a channel higher than a preset level. Thus, the need to provide not less than one filter and detector is eliminated, and the circuit is greatly simplified and miniaturized by adding filter 3 and a logic circuit.