Showing papers on "Clock synchronization published in 1980"

Network Synchronization: Analysis of a Hybrid of Master-Slave and Mutual Synchronization

Abstract: The paper contains a proposal and an analysis of a hybrid method for synchronizing the clocks in a digital switching network to a more select group of "master clocks." The scheme is a hybrid of two well-known techniques, "mutual synchronization" and "masterslave," offering certain unique advantages. It allows different synchronizing disciplines for the masters (such as the toll switching machines) and the remaining subnetwork (composed, for example, of local switches). We begin by considering an idealized model containing only one master with constant clock frequency. The behavior of the controlled frequencies in the subnetwork is described by linear delay-differential equations with the delays determined by distances separating switches. We show that in all cases all clocks in the subnetwork approach in steady state the master clock frequency. Considerable emphasis is placed on the rate of synchronization, as determined by the principal root, the root with largest real part, of the characteristic function of the differential equations. The idealized model is extended in stages. First we consider the effects of many masters with constant but possibly nonidentical frequencies and show that the steady state frequencies in the subnetwork are narrowly bounded. Next, we allow clock drift and the master clocks to fluctuate about nominal centers with given tolerances. An expression for the residual steady-state departures from perfect synchronization shows the tradeoff between transient and stead-state behavior. Finally, two illustrative examples are numerically solved.

Resynchronizing circuit for time division multiplex system

Abstract: The invention relates to input and output circuits for multiplexing equipment, especially the kind used in telephone systems where nominally identical clocking signals have natural deviations of timing (called "plesiochronous" signals). The invention uses the "justification" principle to ensure the clock synchronization of plesiochronous digital signals. A buffer memory, with independent writing and reading capabilities, is formed of two first in-first out or "FiFo" memories connected in series. The request signal for a "justification" is made when a connection is completed between an IR (Input-Ready) output of the second FiFo memory and an input SO (Shift-Out) of the first FiFo memory, if there is an undesirable phase shift between the input and output clocking system. A reading clock oscillator has a frequency which is governed by a governing signal, which depends, at least in part, upon the electrical state existing in the series connection between the IR output of the second FiFo memory and the input SO of the first FiFo memory. The receiving and demultiplexing system uses a similar buffer memory to extract any "justification" signals which were added on transmission. A phase-locked loop including a quartz-controlled oscillator controls the output clocking of the demultiplexer.

Network Timing/Synchronization for Defense Communications

Abstract: The designers of synchronous switched digital communications networks have a large number of possibilities from which to choose a timing/synchronization system. Various combinations of the timing/synchronization system features described here can be used to characterize these possibilities. Advantages and disadvantages of employing different timing/synchronization features are examined, and their relationships to the more commonly discussed mutual and master-slave methods of network timing/synchronization are described. The need for particular timing system options is dependent on system applications. Significant differences in needed capability result from differences between civilian and military application. These differences are discussed, and the relationship between timing/ synchronization requirements of a wartime worldwide synchronous switched digital military communications network and timing system features is explored.

Concurrent carrier and clock synchronization for data transmission system

Abstract: The present invention is directed to circuitry for achieving concurrent synchronization of carrier phase and clock timing in double-sideband, suppressed carrier transmissions systems. A phase-lock loop (PLL) is used in the respective carrier and clock recovery networks. The carrier recovery loop is similar to the conventional "Costas Loop". The PLLs are cross coupled in an interdependent recovery structure to enable a more effective clock and carrier regeneration.

Method and circuit arrangement for clock synchronization in the transmission of digital information signals

Abstract: A method and a circuit arrangement for clock synchronization in the transmission of digital information signals. In the four-wire type transmission of blocks of information signals on a two-wire transmission line it is determined, by phase comparison, whether the first bit in each block of signals (1) falls within a time interval derived from the bit clock signal of the local clock generator; (2) falls within an adjacent time interval or (3) falls within none of such time intervals. Depending upon the results of this comparison, the time relationships are left unchanged, the period of the clock generator is shortened or lengthened one or more times, or a one-time, initial phase equality is established.

Clock synchronization circuit

Abstract: A circuit which monitors the frequency of an incoming signal and synchronizes an internally generated clock signal to the incoming signal. A retriggerable monostable multivibrator monitors the incoming signal which is synchronized by means of a phase lock loop circuit to a signal generated by a voltage controlled multivibrator. A crystal oscillator provides clock signals upon detection of failure of the incoming clock signal.

Guest Editorial: Special issue on synchronization

Abstract: Synchronization is a fundamental problem in digital cornmunications systems. In radar, sonar, and navigation systems, synchronization is connected with the objectives of measuring range, velocity, and position. This Special Issue is devoted specifically to the synchronization problem as it relates to digital communications engineering and technology. In the implementation of digital communication systems, one must distinguish among several types of synchronization. Some of these are: 1 ) carrier synchronization, 2) clock synchronization. 3) codeword and node synchronization, 4) frame synchronization, and 5) network synchronization. This Special Issue provides papers which address each of the above synchronization types. Additionally, special problems related to the operation and performance of synchronizers which employ the phase-lock principle are provided. A brief overview of the content of this Special Issue is presented.

Phase and group delay calibration of a very long baseline interferometer by East Coast VLBI Group

Abstract: Precisely timed pulses injected into the input of each receiver are used to calibrate the phase and group delay through each interferometer terminal The short duration pulses are generated at a 1 MHz rate directly from the output of the frequency standard The pulses are injected into the receiver at a level low enough to produce less than one percent increase in system temperature, yet can be extracted during processing with a high enough signal to noise ratio to determine the phase of the calibration rails within 1 degree in 1 second of integration The calibration system also includes precise cable measurement electronics and a pulse echo for clock synchronization

On Synchronization of Communication Networks with Varying Channel Delays

Abstract: Basic principles which ensure synchronization stability with respect to the delay variation are formulated

Block 1, phase 1 very long baseline interferometry implementation

Abstract: The Block 1, phase 1 VBLI System, implemented in the Deep Space Network and currently undergoing system testing, is discussed The system can be characterized as the modification of existing equipment and the addition of new software in the 64 m subnet and the addition of new hardware and software in the Network Operations and Control Center It is to be operational to support Voyager project navigation requirements and is to provide, on a weekly basis, the information related to station clock synchronization, UT1, and polar motion

Choice of Regulator for Mutual Network Synchronization

Abstract: This paper compares time-discrete regulators used for mutual single-ended synchronization of digital networks. The regulators control the phase differences between clocks in the network nodes. These clocks are disturbed mainly by short-term phase and frequency fluctuations and long-term linear frequency drift. The characteristics of the regulators under study are stability, engineering, and implentation. The main results of the stability analysis are that the P regulator brings about a constant slip rate, the Pl regulator is not slip-free, the Pll 2 regulator is slip-free. With nonzero initial phase differences and jitter, the stability of the regulators containing integrators is secured by not regulating one of the nodes. In conclusion, the Pll 2 regulator is the best choice for single-ended mutual network synchronization.

Pattern selection scanner

Abstract: PURPOSE:To secure the time division by sampling the video output of the pickup tube via the clock pulse of the counter used to the reading scanning system of the information, thus ensuring the reading of the information for the clock synchronization of a high synchronous accuracy. CONSTITUTION:In the address scanning system, both row and column position designation signals SX and SY are converted into the analog signals through D/A converter 1X or 1Y. These analog signals are then sent to horizontal and vertical deflecting circuits 3 and 4 of pickup tube 5 via analog adder 2X or 2Y. The reading scanning system comprises counter 8X which counts the pulse number of clock pulse generator 6 via gate 7X, D/A converter 9X which applies the clock signals to horizontal deflecting circuit 3 via 2X, divider circuit 10 which divides the pulse output cycle of oscillator 6, counter 8Y, and D/A converter 9Y each. And the signal process system consists of video amplifier 11 and sample holding circuit 12.