Showing papers on "Constraint graph (layout) published in 2020"

Self-aligned double patterning-aware routing in chip manufacturing

Abstract: A method of generating a routing result to manufacture an integrated circuit using self-aligned double patterning includes generating an initial routing result that indicates a location and length of connections between components, and generating an initial constraint graph with trim shapes indicating gaps in the connections being represented as nodes and with arcs indicating relative position constraints between a pair of the nodes. The method also includes subdividing the initial constraint graph into two or more subgraphs, determining a final position of each of the nodes in the two or more subgraphs, and generating a routed design with the trim shapes having the final position of corresponding ones of the nodes relative to the connections and with extents filling in spaces between one or more of the trim shapes and associated connections. The routed design is provided for manufacture of the integrated circuit.

Fast Analog Layout Retargeting with Device Abstraction

Abstract: In this paper, we propose a fast template-based analog layout retargeting methodology, which can support general device abstraction and versatile device replacement. In order to achieve high efficiency, the original circuit devices are substituted by abstract devices during the retargeting process. The layout is then retargeted with the aid of a constraint graph, which can not only preserve the layout knowledge, but also tune the device placement by acute user-defined constraints. The retargeted abstract devices are finally replaced by parametrized cells (PCells) to generate the target layout. Our experimental results show that the abstract-device-inclusive retargeting process is much faster than the traditional layout retargeting scheme, and the proposed methodology is general to be applied to any basic analog building blocks and especially beneficial to the radio-frequency (RF) circuits.