Showing papers on "Core router published in 1994"

Method and apparatus for determining a communications path between two nodes in an Internet Protocol (IP) network

Abstract: Method and apparatus for determining a communications path between a source and a destination in an Internet Protocol (IP) network. The method determines a path list of next-hop routers between the source and destination by selecting between a Simple Network Management Protocol (SNMP) query of a current router on the path, and by sending a User Datagram Protocol (UDP) probe packet having a destination field with a destination IP address and a Time-to-Live (TTL) field with a value of one greater than the number of hops to the current router. The steps are iterated until the next router is determined to be the destination. Preferably, the UDP probe packets are loose-source routed through the source. In addition, a topology information database may be accessed to resolve an unknown router, and/or resolve intrarouter devices on the path.

Managing and distributing data objects of different types between computers connected to a network

Abstract: A data management and distribution system has been described that includes router processes for controlling data communications between child processes running on computers connected by a network. Preferably, a router process runs on each computer, with the application processes running on the computer connected directly to the router process. As a result, all interprocess communications must pass through the routers. Each router process includes a connection table listing its connections with all other router and application processes, as well as an interest table listing the type of objects that each of the other processes are interested in receiving. Data communication is accomplished by an application process providing an object to its local router, which then distributes the object to all other interested routers. The object includes a destination list indicating which processes are to receive the object. Thus, with the use of routers, application processes that need to communicate with each other over a network need not know the intricate details (such as the communications protocol used, the exact address of the receiving process, etc.) involved in transmitting information. By placing the burden of managing the network communications on the local routers, the complexity of the application code is reduced since it has only a single connection to its local router.

EIGRP--A Fast Routing Protocol based on Distance Vectors - eScholarship

Abstract: EIGRP{A FAST ROUTING PROTOCOL BASED ON DISTANCE VECTORS Bob Albrightson Cisco Systems Menlo Park, CA 94025 albright@cisco.com J.J. Garcia-Luna-Aceves University of California Santa Cruz, CA 95064 jj@cse.ucsc.edu Joanne Boyle Cisco Systems Menlo Park, CA 94025 boyle@cisco.com Abstract Early routing protocols were based on distance vectors; they were very simple and easy to implement but had the severe drawbacks of counting to innity and routing loops. These problems were reduced using such techniques as split horizon and hold-downs; however, for these techniques to work in practice, long convergence times are introduced. Routing protocols based on link states have been implemented to address the problem of slow convergence in distance-vector protocols, but they add complexity in conguration and troubleshooting. We present a new distance-vector protocol that converges as quickly as current link-state protocols, while maintaining loop freedom at every instant. The protocol is based on three main elements: a transport algorithm that supports the reliable exchange of messages among routers, the diusing update algorithm, which computes shortest paths distributedly, and modules that permit the operation of the new routing protocol in a multiprotocol environment. 1 INTRODUCTION Today's intradomain routing protocols can be classied as distance-vector or link-state protocols. In a distance-vector protocol, a router knows the length of the shortest path from each neighbor node to every network destination, and uses this information to compute the shortest path and next router in the path to each destination. A router sends update messages to its neighbors, who in turn process the messages and send messages of their own, if needed. Each update message contains a vector of one or more entries, each of which species, as a minimum, the distance to a given destination. In contrast, in a link-state protocol a router must receive information about the entire topology to compute the shortest path to each destination using a local shortest-path algorithm such as Dijkstra's algorithm [1]. Each router broadcasts update messages, containing the state of each of the router's adjacent links, to every other router in the network. The distance vector protocols used in the Internet thus far are based on variants of the distributed Bellman-Ford algorithm (DBF) for shortest-path computation [1]. The primary disadvantage of DBF is that incorrect entries in routing tables may form routing-table loops for one or more destinations whenever link costs increase [9]. Because a router chooses as its successor to a destination any neighbor router who appears to oer the shortest path to that destination, the router may choose paths that lead to loops for as long as those neighbor routers with viable paths to the destination oer path lengths longer than those paths leading to loops. The worst case of this problem is rather severe: when routers fail or the network partitions, a router can detect such events only after it has considered all possible path lengths to the one or more destinations that have become unreachable through any of its neighbors. Accordingly, this

The Chaos router

Abstract: The Chaos router, a randomizing, nonminimal adaptive packet router is introduced. Adaptive routers allow messages to dynamically select paths, depending on network traffic, and bypass congested nodes. This flexibility contrasts with oblivious packet routers where the path of a packet is statically determined at the source node. A key advancement of the Chaos router over previous nonminimal routers is the use of randomization to eliminate the need for livelock protection. This simplifies adaptive routing to be of approximately the same complexity along the critical decision path as an oblivious router. The primary cost is that the Chaos router is probabilistically livelock free rather than being deterministically livelock free, but evidence is presented implying that these are equivalent in practice. The principal advantage is excellent performance for nonuniform traffic patterns. The Chaos router is described, it is shown to be deadlock free and probabilistically livelock free, and performance results are presented for a variety of work loads. >

Generic managed object model for lan domain

Abstract: An internetwork system has several interlinked computer networks, each network having an associated element manager (16) which is arranged to communicate with a router via a first network management protocol. Each element manager (16) has means for converting from the first network management protocol to a second protocol and also has means for communicating via the network manager (20). The network manager (20) allows a user of the system to control a router by issuing a command at the network manager and/or to view information on the status, configuration and/or performance of the router.

Ariadne—an adaptive router for fault-tolerant multicomputers

Abstract: Adaptive routing has been proposed as a means of improving performance and fault-tolerance in multicomputer networks. While a number of algorithms have been proposed, few adaptive routers have been implemented in hardware. This paper presents the design and implementation of Ariadne --- a prototype single chip, hardware router. The primary motivation is tolerance to link and router failures, while reconciling conflicting demands on performance. This is achieved by implementing the m-misroute backtracking protocol (MB-m) using the pipelined circuitswitching (PCS) communication mechanism[17]. Ariadne implements two virtual data channels and one virtual control channel per physical link. The router is self-timed with single flit buffering at the input and output ports, and is fully adaptive.

On the Design of a Multigigabit IP Router

Abstract: The emergence of gigabit speed networks hinges upon the existence of high performance internetworking units, such as IP routers. In this paper, we present an architecture and we discuss the implementation of a multigigabit IP router. For this implementation, two special purpose VLSI chips are required; the rest can be built using off-the-shelf components. IP header processing of received packets is handled by a specialized chip. Memory management, another well-known performance bottleneck, is simplified and efficiently implemented using special VLSI support. Searching for the next hop address in the routing table, which is the major contributor to the delay in traditional IP protocol implementations, is significantly reduced by using a special configuration of Content Addressable Memories (CAMs).

FA 18.4: a phase-tolerant 3.8 GB/s data-communication router for a multiprocessor supercomputer backplane

Abstract: Recent parallel processor supercomputer designs use an active backplane of routers to form the interconnections between processing elements. Today, high-bandwidth interconnect systems capable of scaling to configurations with more than 500 processing nodes tend to use self-timed designs. This avoids clock distribution problems seen in large phase-sensitive synchronous systems. The BiCMOS routing component described in this paper employs 200 MHz clocked communication for large scalable parallel-processor supercomputer systems. This scheme eliminates need for clock edges to be phase-aligned across the clock distribution network. Additionally, router inputs accept data at any phase relationship to the receiving router internal clock. >

Segment router: a novel router design for parallel computers

Abstract: In this paper we present the Segment router, a novel router design for the interconnection networks of massively parallel computers. The design decisions of the Segment router are motivated by the need to improve the network performance when the traffic consists of messages with widely different lengths.The key novelty of the Segment router is that it provides different queueing policies for the two classes of messages it services. Short messages are stored in a centralized, dynamically allocated queue that guarantees storage availability for the whole packet of the short message. Long messages on the other hand are stored in small FIFO buffers associated with the input channels of the router. Thus when a long message becomes blocked, it is stored in segments in the FIFO buffers of a number of routing elements in the network. Furthermore, the physical channels of the Segment router are fairly multiplexed between the two supported classes of messages without the potential for starvation.Using simulations we compare the performance of our technique to the performance of multipacket messages and networks implementing lanes. The results clearly demonstrate the performance advantages of our technique.

Parallel computer system including arrangement for quickly draining messages from message router

Abstract: A computer including a processor array and a routing network. Processors in the processor array generate messages for transfer to over the routing network, each message including a path identifier portion identifying a path from a source, message processor to a destination processor. The routing network comprises a plurality of interconnected router nodes, at least some of said router nodes being connected to the processors to receive messages therefrom and transmit messages thereto. Each router node operates in a plurality of modes. In a first mode, the router nodes couple received messages to a router node connected thereto in accordance with the path identifier portion to thereby transfer each respective message along the path identified in its path identifier portion. In a second mode, the router node couple received messages to predetermined ones of the router nodes or processors connected thereto, the predetermined ones of said router nodes or processors being selected to facilitate transfer of a message to a nearby processor to facilitate the rapid emptying of the routing network of messages. A control element controls the router nodes to enable them to operate in the first mode or second mode generally contemporaneously.

A VLSI CAM-based flexible oblivious router for multiprocessor interconnection networks

Abstract: A VLSI implementation of a flexible router scheme for parallel interconnection network architectures is presented in this paper. The router implements implicit oblivious routing algorithms in 1.5 clock cycles, this being the fastest approach for flexible routers. To further increase performance, the router operation has been made pipelined with a throughput of 1 routing decision per cycle. The implementation is based on a combination of a content addressable memory that supports per entry unique bit masking, a fast priority scheme that allows only one entry to be selected, and a memory that stores the port assignment. The number of required CAM entries is extremely small; it is of the same order as the output ports (or node degree). >

Local Network Interconnection System for Long Distances

Abstract: The system includes a first local network (LAN1) which is connected to an extended network (WAN) by a routing/bridge network (BR1). The first local network includes a number of stations (ST1,ST2). A second local network (LAN2) has a server (SV) and is connected to the extended network by a node (N2). The node has an active router/bridge (BR3). The bridge emits digital word frames and surveillance frames to its local network. The node has a second router bridge (BR3) which monitors transmissions from the active router/bridge. The second router/ bridge becomes operative if the first router/bridge is found not to be active when the first network routes to the second.

SNMP Application for the MINT Router (Walkstation II project)

Abstract: The purpose of the Walkstation II project is to create a testbed for a wireless communication system with access to the Internet. The Mobile INTernet (MINT) router is a core element of this project. Most of the routers and many other nodes of today's Internet support network management. This includes the remote control of various parameters which caracterize the status of physical interfaces, protocols and many other objects. The Simple Network Management Protocol (SNMP) which was used in the current work is a standard protocol of the TCP/IP suite. All the managed nodes of the Internet have a common set of management capabilities. Their implementation is available in software development packages. The management of mobile stations requires a new set of management capabilities. They will allow for the control of mobility support and the radio links. The current work consists in adapting the set of standard SNMP capabilities to the MINT router and of the creation of a set of new capabilities specific to the MINT.

An Adaptive Router for Fault-tolerant Multicomputers

Abstract: Adaptive routing has been proposed as a means of improving performance and fault-tolerance in multicomputer networks. While a number of algorithms have been proposed, few adaptive routers have been implemented in hardware. This paper presents the design and implementation of Ariadne - a prototype single chip, hardware router. The primary motivation is tolerance to link and router failures, while reconciling conflicting demands on performance. This is achieved by implementing the m-misroute backtracking protocol (MB-m) using the pipelined circuitswitching (PCS) communication mechanism[l7]. Ariadne implements two virtual data channels and one virtual control channel per physical link. The router is self-timed with single flit buffering at the input and output ports, and is fully adaptive.

Design of adaptive mesh routing chip

Abstract: Design of an adaptive router chip with minimum possible delay is described. The designed router is for message passing between computers which are connected in 2D mesh topology. The implemented algorithm is the negative-first adaptive wormhole routing algorithm which is deadlock free, livelock free, minimal, and maximally adaptive. The functional blocks of the router and asynchronous interfaces between routers were verified with VHDL modeling and simulation. Future enhancements for dynamic fault handling features are discussed. >