Showing papers on "Decimal published in 1984"

The decimal scale for relevés of permanent quadrats

Abstract: For vegetation analyses of permanent quadrats the author formerly used a modified scale of Braun-Blanquet with smaller intervals than in the original. For calculations of difference- and change quotients etc., on the basis of coverage, the symbols of this scale have to be converted to values proportional to the real coverage percentages. A conversion in simple terms is not possible; so the calculations are inconvenient. For an efficient analysis of permanent quadrats a scale is needed that fulfils some requirements. The decimal scale fulfils these. For the analysis of small sub-quadrats of a permanent quadrat a coarse scale is proposed. This scale is directly comparable with the finer decimal scale.

Guiding children's learning of mathematics

Abstract: Part I: Foundations for teaching mathematics: Mathematics today for elementary schools Foundations for planning effective teaching Organizing for instruction Assessment in elementary school mathematics. Part II: Four general standards: Mathematics and problem solving Communication, reasoning and connections. Part III: Procedures and materials: Early experiences with mathematics Extending understanding of numbers and numeration Teaching addition and subtraction of whole numbers Teaching multiplication and division of whole numbers Informal geometry Fractional numbers common fractions Fractional numbers Decimal fractions and percent Measurement Tables, graphs, statistics, and probability.

Apparatus for decimal multiplication

Abstract: An apparatus for decimal multiplication divides a multiplier of binary coded decimal (BCD) into plural groups, generates plural partial products of which are multiplied a multiplicand of BCD and the plural groups of multiplier over successive cycles and adds them to an intermediate product which is a summation of the previously generated partial products. The addition of the partial product and the intermediate product is made by a carry save adder. At a first cycle, the intermediate product is set to zero, and the addition of 6 is made to each digit of either one of the intermediate product sum and the partial product, and the addition of the partial product and the intermediate product is made by a carry save adder loop over successive cycles. At a final cycle, the sum and carry from the carry save adder are added by a full adder, and the subtraction of 6 is made for each digit according to the existence of carry transfer in each digit of the full adder and the resultant value is output as a multiplication result.

Coded decimal non-restoring divider

Abstract: This invention employs a construction in which subtraction processing and digit shift processing in decimal division are carried out in parallel with each other to shorten the time required for decimal division. A dividend is stored in a register B and a divisor, in a register C. A selector 6 selects register B when the result of subtraction by an adder/subtracter 1 is positive or zero, and selects register A at other times. Both adder/subtracter 1 and a shifter 2 receive the signal from the selector 6 in the same way, and execute the subtraction processing and the shift processing, respectively. The results of these processings are stored in the registers B and A', respectively. The division time can be shortened because the adder/subtracter 1 and the shifter 2 can be actuated simultaneously.

A new method for coin flipping by telephone

Abstract: A new one-way function that permits generation of random events is presented. This one-way function is based on decimal sequences.

An Overview of Factoring

Abstract: During a meeting of the American Mathematical Society in 1903, Cole silently demonstrated, to considerable acclaim, that 267−1=193707721·761838257287, where each of the two numbers on the right hand side is a prime. This result took him “three years of Sundays” to calculate by hand. Today the factorization of a mere 21 digit number would not occasion any special notice. This is because of the development of very fast computing devices and a concomitant development and refinement of methods of factoring which can, be used on these machines. Recent examples of spetacular factorizations include 2211−1=15193·60272956433838849161·P40, 2256+1 = 1238926361552897·P62, 2267−1=535006138814359·1155685395246619182673033·P39, where all factors on the right hand side are primes and Px denotes a prime of x decimal digits.

Precise Scientific Computation with a Microprocessor

Abstract: When a high-level programming language is used for scientific computation, usually one must use standard floating point and choose the precision?single, double, or higher?before one's program executes. This paper describes a modified Basic that accommodates the advanced computation techniques of dynamic adjustable precision and interval arithmetic. This language?Precision Basic or Pbasic?allows a user to routinely obtain his n decimal place answers accurate to the last decimal place. An interpreter for this modified Basic was recently completed that runs on a Z-80 microprocessor. Some features of the interpreter are described.

Diagnosis and prescription in the classroom : some common maths problems

Abstract: The Need for Diagnosis The Natural Numbers Small Numbers Decimal Fractions Small Numbers Common Fractions Percentage, Ratio and Proportion Shape and Form Similarity The Circle and its Measurement An Introduction to Algebra Statistics On Average Problem Solving Context, Attitude and Anxiety Adults and Numeracy Teaching Maths

Apparatus and method for converting a number in binary format to a decimal format

Abstract: A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is described. The CPU includes a microprocessor which executes the binary arithmetic software instructions under firmware control. The CPU also includes commercial instruction logic which is used in conjunction with the microprocessor to execute decimal arithmetic operations. The commercial instruction logic also operates under firmware control with the addressing of the firmware microinstructions being controlled by the microprocessor. Also disclosed is the method by which the CPU performs decimal addition, subtraction, multiplication and division arithmetic operations and the method used to convert a number in a binary format to a number in a decimal format and the method used to convert a number in a decimal format to a number in a binary format.

Corrections to Millett's table of electromagnetic coupling phase angles

Abstract: Millett (1967) published tables of values of the mutual impedance due to inductive coupling between two collinear dipoles on a uniform, nonpolarizable half‐space. In the course of a recent study (Brown, 1984) I have noticed significant errors, of two different kinds, in the phase angles (ϕ) given by Millett (1967). One kind of error is evidently typographical in nature and occurs only twice, in the M = 3 table, for θ = .01 and .02. The tabled values apparently had their decimal points shifted one place. The second and more serious kind of error is an apparently random error within the range ±0.003 degrees. This is not significant for larger |ϕ|, say |ϕ| > 1 degree, but the values of |ϕ| in Millett’s tables go down to 0.006 degrees (down to 0.0045 degrees after correction) where such errors are clearly significant, particlarly if one is working with logarithmic quantities as is common.

All numbers great and small

Abstract: Some time around 760 A.D., an Arabian mathematician called al-Khowarizmi wrote a book outlining the rules for performing basic arithmetic using numbers expressed in the Hindu decimal form that we use today, with columns for units, tens, hundreds, etc., and decimal points to denote fractions. From his name comes the modern word ‘algorithm’, nowadays used to describe any set of rules for performing calculations. Computer programs are just algorithms expressed in some computing language such as BASIC, FORTRAN, or PASCAL. (At least, computer programs concerned with mathematical calculations are algorithms. In other cases it may or may not be the case that an ‘algorithm’ is involved.)

Operation processing system

Abstract: PURPOSE:To shorten the number of steps, and also to omit recorrect-processing, by providing a circuit for detecting which is necessary, substantial addition or substantial subtraction. CONSTITUTION:An augent or a minuend X is set to an X-register 1 through a line 101, and an added or a subtrahend Y is set to a Y-register 2 through a line 102, so that a code comes to the right end, respectively. Also, a line 100 is set to ''0'' and ''1'' at the time of addition and subtraction, respectively. Decimal addition and subtraction execute a classification of an operation to be executed to a code of a result and an absolute value, namely, bracketing of X+Y, X-Y or -X+Y, by the first step, and its operation is executed and a code is generated by the second step.

Conversation type scheduler

Abstract: PURPOSE:To decrease the operating time, by adding decimal points with registration when hour is fed and therefore discriminating the decimal point input to omit the setting of minute. CONSTITUTION:A conversation type scheduler is controlled wholly by a CPU 9. When an electrical power supply is turned on, an READ signal is applied to a timing part 13 from the CPU 9. Then the TIME obtained by the present time given from the part 13 is read in and displayed at a display 1 to obtain a key input waiting state of a keyboard 2. Then an ROM 10 and an RAM 11 are used with operation of both a mode key and a schedule declearing key which set the schedule of the keyboard 2, and the operations of these ROM 10 and RAM 11 are discriminated and displayed to the display 1. Then hour is fed with operation of the declearing key for application of a timepiece. In this case, the CPU 9 discriminates the operation of a register key and a decimal point key, and the minute setting is omitted with a decimal point input with a display at the display 1. Thus the operating time is decreased for a conversation type scheduler, and each schedule is stored in schedule memories 121-12n respectively.

Decimal arithmetic device

Abstract: PURPOSE:To eliminate the need for a format converter and to shorten an arithmetic processing time, by processing two kinds of data, i.e. packed data and unpacked data without converting decimal data from an unpacked format to a packed format. CONSTITUTION:A means for processing two kinds of data, i.e. packed and unpacked data without converting unpacked decimal data into packed data is provided. For example, the low-order two digits of an operand are inputted to a device 100 which receives the 1st operand and a device 101 which receives the 2nd operand, and the zone part of the output of the device 100 is corrected into a specific constant by selecting devices 102a and 102b on the basis of the data format and information from an arithmetic mode display device 105. The corrected value from the selecting devices 102a and 102b and the output of the device 101 are processed by decimal computing elements 104b and 104d, and a zone code is inserted into zone parts of their outputs by selecting circuits 103a and 103b on the basis of information from a data format display device 106.

Confirming method for quality of output data

Abstract: PURPOSE:To confirm correctly whether the data delivered from a processor is received correctly by an external device by taking an error of conversion into consideration. CONSTITUTION:The parameter stored in a parameter memory 104 is converted into a decimal number and then recorded on a paper tape 107 serving as an external memory means. Then an output data quality confirming switch 105a is turned on to set an NC device in an output data quality confirmation mode. A processor 101 reads successively the parameters recorded on the tape 107 and at the same time converts a decimal number into a floating point to store the decimal point in a data memory 103. Then the processor 101 compares the parameters stored in the memories 104 and 103 with each other. In this case, the comparison error factor is decided correct if it is less than the prescribed value obtained with consideration given to the error of conversion. In such a way, it can be confirmed correctly whether the data delivered from the processor is received correctly by an external device.

Digital valve control device

Abstract: PURPOSE:To attain highly advanced numeral processing also by a sequencer omitting decimal/binary conversion by supplying setting outputs from digital switches directly to adaptors to set up numerals for controllers controlling digital valves CONSTITUTION:A control unit 1 is formed by the controllers 11a, 11b controlling the digital valves on the basis of table information determining the control variables of the valves and table information determining the moving patterns of the valves and the adaptors 12a, 12b converting a decimal code input to a binary code The digital switch groups B1-Bn setting up the control variable and moving pattern of the valve set up on an operation panel are connected to the adaptor The output of a programmable sequencer 2 is also connected to the controller 11a to specify table information by a digital switch through the adaptors and to control the digital valve 5 automatically in accordance with a command by a controlling means from the programmable sequencer 2 to the controllers

Access processing system of data arrangement

Abstract: PURPOSE:To attain the high class language processing in high speed, by provding an index register handling only a decimal number, and omitting decimal-hexadecimal conversion for data referencing, rewriting and transferring for executing them with parameters of decimal number conversion. CONSTITUTION:Data are stored in an index register 1 handling the decimal number only and they are summed 2 with a head address (a) of the arrangement A and stored in an address register 3. Further, the parameter of the hexadecimal mode or the address at normal memory access are stored in the address register 4. A multiplexer 5 selects one of the address registers 3, 4 with a mode switching signal MS, the content is extracted on a bus 7 and addressed to the arrangement A in the memory. It is impossible for areas 9, 10 to access the decimal parameter, and they are used for other applications. The result of access of the decimal parameter is read out from a bus 11 as data b1, b2. Thus, the decimal- hexadecimal(binary) conversion is omitted and the processing using the high class language is quickened.

Binary-decimal converting circuit

Abstract: PURPOSE:To simplify a constitution and to attain high-speed processing by performing a binary-decimal operation just with a decimal total addition. CONSTITUTION:A binary input to be converted with a command of a controller 4 is loaded to a shift register 1, and at the same time a temporary memory register 2 is reset. While the output 34 of a decimal adder 3 delivers the value obtained by doubling the contents of the register 2 and the value obtained by adding the present highest bits of the register 1. Therefore the first output D0 of the adder 3 is set as D0=Dn (Dn: the highest bit of the register 1). Then the D0 is loaded to the register 2, and at the same time the register 1 is shifted toward an MSB by a bit. As a result, the next output D1 is set as D1=bnX2+bn-1. Thus an output Dn is obtained through conversion of a binary number into a decimal number by repeating the above-mentioned operations by a frequency equal to the bit number (n) of the binary input.

Display circuit of frequency unit

Abstract: PURPOSE:To confirm a reception frequency and its unit at a look by providing light emitting elements corresponding to display characters which indicate frequency units of respective reception bands, and switching and turning on the light emitting elements by utilizing a decimal-point output CONSTITUTION:When the decimal-point output terminal DP of a driving circuit 5 goes up to a level H, a transistor TRQ1 turns on and a light emitting diode D1 turns on, so that a frequency display device 3 displays a frequency on MHz basis At this time, a TRQ2 turns off and a light emitting diode D2 is still off When the terminal DP is at a level L, the TRQ1 turns off, the TRQ2 turns off, and the light emitting diode D2 turns on, so that the display device 3 performs kHz display Namely, when those frequency units are changed, the reception frequency of FM, SW, etc, is displayed together with the decimal point like 9810MHz and that of MW, W, etc, is displayed without the decimal point like 1,424kHz

Data transmission and reception system

Abstract: PURPOSE:To attain data transmission and reception with high reliability by making a code group usable for each of parallel signals of plural times different entirely from a code group usable for other parallel signals to discriminate codes at what number of times it is transmitted. CONSTITUTION:Four output ports of a microcomputer 11 and four input ports of a microcomputer 12 are connected by four buses. One word is transmitted and received by using two times of 4-bit parallel signals. A code transmitted from the microcomputer 11 by the 1st 4-bit parallel signal is one of 10-15 of decimal number representation and a code transmitted by the 2nd 4-bit parallel signal is one of 1-9 in decimal notation. Thus, the 1st or the 2nd code is discriminated without providing any control line.

Numerical train converting system

Abstract: PURPOSE:To realize hexadecimal and binary conversions by a compact circuit which combines simple parts by selecting an extended representation of a decimal number with a zone CONSTITUTION:For instance, a hexadecimal numerical train 1, A, B, 9, F, C, E, D is inputted to a translating circuit 1 in the form of an EBCDIC code train F1, C1, C2, F9, C6, C3, C4 The translating circuit 1 refers to a translation table 3, and outputs after converting it to a decimal number with a zone and its extended representation F1, FA, FB, F9, FF, FC, FE, FD Subsequently, a packing circuit 2 eliminates a zone part F of each character and converts it to a binary number In a decimal number pack, a code is required for the minimum place digit, therefore, a suitable temporary code is put on so as to be discarded in the end As a final result, a binary numerical train 1AB9FCED is obtained

Half-rounding arithmetic system of real number output conversion

Abstract: PURPOSE:To eliminate the need for multiplication and division for finding a half- rounded value, by providing a scaling part for scaling input converted data in binary representation to a value within a specific range. CONSTITUTION:The scaling processing part for scaling input converted data in binary notation to a value within the specific range is provided. For example, the scaling processing part 4 of a binary-decimal conversion processor 2 extracts the converted data (x) from an input data file 1 to perform scaling processing and outputs the scaled value and the number K of digits of an integer part. Then, a half-rounded value table address calculating part 5 calculates an address of a table from the number K of digits of the integer part and the number L of converted digits to access a half-rounded value table 6. Then, the half-rounded value DELTAx read out of the half-rounded value table 6 and the scaled value X are added to each other by an adding part 7, whose addition result X+DELTAx is converted from binary to decimal and stored in an output data file 3.

Code conversion system

Abstract: PURPOSE:To perform the code conversion at a high speed, by adding overflowed bits to the second register and storing the result as a binary-coded decimal number in a decimal correcting means CONSTITUTION:The binary number stored in the first register R1 is shifted left by one digit, and the first bit is stored in a carry bit memory C Contents of the second register R2 where a binary-coded decimal number is stored are doubled by an arithmetic device AD to add the overflowed carry bit The result is stored as a binary-coded decimal number in the register R2 by the decimal correcting means, and this operation is repeated by the number of times corresponding to the number of all bits of the register R1 After repeating this operation, a binary-coded decimal number is attained in the register R2

Denary logic arithmetic processor

Abstract: When the binary system is used to perform decimal calculations, code-to-code conversion is inevitable. But with denary logic, such conversions can be eliminated. The construction philosophy of the experimental arithmetic processor is similar to that of a microprocessor. Although the circuit elements are mostly binary types, owing to the lack of denary logic elements, the feasibility of performing arithmetic operations directly with the base of 10 is clearly demonstrated.

Binary-decimal converting system

Abstract: PURPOSE:To reduce the number of times of operation by decomposing binary data into blocks, each of which consists of a preliminarily determined number of bits, in order from the least significant bit and storing these blocks and converting blocks to decimal data in order from the low-order block and shifting up data in accordance with positions occupied by blocks to add data successively CONSTITUTION:First, counters 10 and 15 are cleared to 0, and binary data in a register 14 is transferred to a shifter 18 through a selecting circuit 16 and an adding circuit 17, and, for example, the lowest 4 bits of data are sent to a latch circuit 12 A corresponding address of a converting circuit 13 is accessed in accordance with contents of the latch circuit 12 and the counter 10 to convert this 4-bit data to decimal data, and this decimal data is added to contents of the register 15 by the adding circuit 17, and the result is shifted by the shifter 18 and is stored in the register 15, and the counter 10 is counted up Next, binary data from the register 14 is transferred to the shifter 18, and the next lowest 4 bit are subjected to the similar processing This operation is repeated to convert binary data in the register 14 to decimal data, and decimal data is stored in the register 15 Thus, the number of times of converting operation is reduced to 1/4

Decimal adder/subtractor

Abstract: PURPOSE:To shorten instruction executing time and to improve the performance of the titled circuit by adding/subtracting a 9-bit byte pack type decimal number as the 9-bit byte format without data conversion from 9 bits to 8 bits. CONSTITUTION:The adder/subtractor 9 receives the output of a selecting circuit 6 as a left input through a signal line 102 and the output of a selecting circuit 7 as a right input through a signal line 103 to add/subtract a 9-bit byte pack type decimal number. The decimal adder/subtractor 9 is constituted by a decimal adder/subtractor group 20-1-20-8 for 4 bits, a binary adder group 21-1-21-4 for one bit which receive the uppermost bit of each 9-bit byte as the 1st input and the inverted output of the uppermost bit as the 2nd input and a carrying foresight circuit 22. A carrying generating output and a carrying transmitting output from the binary adder group 21 and the decimal adder/subtractor group 20 are inputted to the carrying foresight circuit 22 to form a carrying input to the decimal adder/subtractor group 20. A ''0'' coupling circuit 10 couples ''0'' with the upper one bit of each 8-bit byte output from the adder/subtractor 9.

Electronic typewriter with arithmetic function

Abstract: PURPOSE:To prevent the erroneous recognition of full stops mark by key input just before line feeding for decimal points by a method in which only when key input just before full-stop mark key is numeral key, it is regarded as decimal point and processed arithmetically in the line to follow. CONSTITUTION:In a step 25, whether data by key input are carriage return or not is judged. In the case of carriage return, in a step 27, whether data by key input just before carriage return are full stops or not is judged. In the case of full stops, in a step 28, whether data by key input just before the full stops are numerals or arithmetic marks is judged. In the case of numerals or arithmetic marks, the step 21 is again entered. The erroneous recognition of the full stops by key input for showing the end of sentences just before line feeding by the carriage return for decimal points can thus be prevented and exact arithmetic processing can be made.