Showing papers on "Design for testing published in 1978"

A Technology-Relative Computer-Aided Design System: Abstract Representations, Transformations, and Design Tradeoffs

Abstract: This paper discusses the approach to global optimization taken in the C-MU register-transfer level computer-aided design system, currently under development at Carnegie-Mellon University, and gives examples of its application.

Register-Transfer Level Digital Design Automation: The Allocation Process

Abstract: This paper presents a portion of the register-transfer level computer aided design (RT-CAD) research at Carnegie-Mellon University. This part of the research involves the design and construction of an allocator, consisting of a set of algorithms and data structures which synthesize hardware at the logical level from a behavioral description. Preliminary results indicate the allocators performance compares favorably with a human designer.

LSI chip design for testability

Abstract: The design of LSI chips for testability using shift register latches as the basic storage units in level sensitive scan application will be discussed. Examples of circuits using this technique will also be offered.

Practical design of low-cost large space structures

Abstract: The practical design of low-cost space structures involves the use of approaches that reduce the cost of the design and development effort itself. Such approaches include: (1) design with criteria arrived at rationally; (2) design for simplicity, repeatability, and modularity; (3) assembly without adjustments; (4) design for testability on the ground; (5) the attainment of structural efficiency by configuration and material choice rather than by squeezing down on the design margins; and (6) prefabrication and preassembly before launch. Attention is given to truss platform designs, and the Seasat Extendible Support Structure is discussed as a particular example.

Avionics design for testability an aircraft contractor's viewpoint

Abstract: Designing avionics for testability is the inclusion of design provisions in the avionics to enable test of the performance capability of the avionics, to isolate avionic malfunctions to replaceable elements, and to permit adjustment and alignment of the avionics as may be required. The effective implementation of testability provisions in the design of the Air Vehicle Equipment (AVE) and the Ground Support Equipment (GSE) that comprise the avionics can improve equipment reliability and availibility while reducing equipment weight and cost. Accordingly, the operational readiness of the weapon system can be improved by effectively designing the avionics for testability. The aircraft contractor's viewpoint of designing avionics for testability is presented along with the methods and techniques employed by the aircraft contractor to effectively include testability provisions in the avionics.

Design-to-cost: the road to testability

Abstract: Operation and Support (O&S) costs account for an ever increasing share of weapon systems budgets. Maintenance costs are a major driver in the 0 & S cost equation. As a result, testability, as a subset of maintainability, has become of increasing concern not only to the test community, but to the weapon system designer as well. While acceptance of the notion of testability poses no serious difficulty, the methodology of its delineation and measurement requires both definition and a means of implementation. While any number of parameters can serve to characterize elements of testability, any of these is utlimately translatable to cost. It is therefore suggested that the concept of testability be addressed within a Life Cycle Cost (LCC) structure, and reduced to practice by the application of Design To Cost (DTC) tech niques.

Avionics design for testability a vendor's viewpont

Abstract: Historically, testability of new avionic systems has been accorded a rather low priority by de sign engineers who were also concerned with more easily measured parameters such as sys tem performance, reliability, or ability to op erate in harsh environments. Generation of Test Requirement Documentation and calculation of the Shop Non-Ambiguity Ratio for a Unit Under Test provides a means of measuring the testability of that UUT. For digital circuit modules, this ef fort can be automated through the use of ATE with circuit simulation capability. With eight years experience in generating TRD's for several systems, GE has found that UUT's are more testable when designed by engineers who have been involved with TRD generation and validation than when they are designed by en gineers with no TRD experience. While test ability assessment and enhancement efforts usually extend development schedules and add to the cost of avionic systems while reducing their reliability, the negative impact on a development program can be minimized by utilizing a special ized team of testability/maintainability engineers to perform the testability assessment and en hancernent efforts in parallel with the system de sign engineers at the very beginning of the devel opment program before the system design is firmly documented by issuance of a drawing structure.

Fault detection of MOS combinatorial networks

Abstract: Since the technology has gone into large and very large scale integration (LSI and VLSI), one important problem is the testing of such integrated circuits. Recently, increasing interest and attention has been given to “design for testability” or design of diagnosable digital networks.Computer algorithms for designing diagnosable metal oxide semiconductor (MOS) networks have recently been presented by these authors. In this paper, we discuss the testing aspect of these designed networks.A basic cell model was presented for the purpose of simulation and test generation. Procedures for describing the generation of a complete fault detection set for the complex cell are given. Both minimal and near-minimal solutions are presented for both fan-out free and arbritrary complex cells respectively. Also, a procedure for generating the fault detection test list for arbitrary combinational networks is given also.Some future work problems are presented and the application of this design technique for improving the LSI and VLSI testability is introduced.