Showing papers on "Effective number of bits published in 1984"

System for multiple error detection with single and double bit error correction

Abstract: A system for detecting multiple errors that may occur during transfer of data and for correcting up to two of these errors simultaneously. The system has a component for calculating a number of check bits associated with the data word. Also provided is a component for grouping all data bits into base groups and multiple groups, the sum of the number of base groups and multiple groups being equal to the number of check bits. Up to two weights are assigned for each data bit. The system distributes the data bits among the groups according to the weights assigned thereto. Also provided is a component for generating a check bit for each of the groups and for padding the data word with the check bits to form an appended data word. A generator creates a predetermined number of syndrome bits, the number being the number of check bits. Finally, a decoder is provided for decoding the syndrome bits to identify the erroneous bits in the data word.

Digital sum value corrective scrambling in the compact digital disc system

Abstract: A method and apparatus for recording and reading information in the form of a track of pit and land areas on an optical digital disc record carrier. The information is first encoded from symbol blocks of data bits into symbol blocks of channel bits to which are added merging bits selected so as to minimize the d.c. unbalance or digital sum value of the channel bits. Those parts of the stream of channel bits for which the d.c. unbalance does not meet predetermined criteria are subjected to selective scrambling to correct such unbalance prior to recording. During read-out the correctively scrambled parts of the recovered symbol blocks of data bits are descrambled in an inverse manner. Information identifying such parts is recorded with the channel bits. The invention also relates to a record carrier on which information has been so recorded.

Two-step switched-capacitor digital to analog converter

Abstract: In accordance with the present invention, the circuitry of the ten bit switched capacitor digital to analog converter utilizes five binary weighted input capacitors and a digital circuit to perform multiplexing and generating the necessary timing. A combination of input capacitors and feedback capacitors give rise to an output voltage in an amount proportional to digital input bits in a binary fashion such that in the first step, the output voltage is proportional to the first five least significant bits divided by 32 and the second step the output voltage would be equal to the previous value plus a voltage proportional to the five most significant bits. Therefore, at the end of the second step, the output voltage is an analog voltage proportional to the binary input bits times the reference voltage divided by 1024.

Effective Bits: Is That All There Is?

Abstract: The number of effective bits is becoming accepted as an overall measure of dynamic performance for analog-to-digital converters and waveform recorders. However, units with the same number of effective bits can respond very differently to waveforms of identical input data.

Digital data recording and reproducing device

Abstract: OF THE DISCLOSURE A digital data recording and reproducing device is disclosed, an operation of error detection is performed with respect to data with weighting provided with a code word dissolution of M bits in upper m1 bits of the most significant bit side of great weighting and lower m2 bits of the least significant side of small weighting. Error concealment is done for each of these error detections. When reproducing data at a different tape speed from that at the time of recording, an operation of detecting an error in lower m2 bits is inhibited, and the reference of judgement of an error in the data is altered.

Circuits for detecting framing bits in a t.d.m. bit stream

Abstract: A framing circuit is disclosed for detecting framing bits in a t.d.m. bit stream having an extended DS1 framing format. The circuit comprises a RAM for storing in respect of each of the 772 time channels the five most recent information bits of the time channel and three other, candidate, bits which represent the likelihood that the particular time channel carries the framing bit pattern. The current and five stored information bits of each time channel are checked to detect the six-bit framing bit pattern. The candidate bits have their value increased or decreased, within predetermined limits, in dependence upon whether or not a phase of the framing bit pattern is detected, and the updated information and candidate bits are stored in the RAM. The modification of the candidate bits in this manner is effected in only every third 772-bit frame. A framing signal is produced in dependence upon the candidate bits.

Apparatus and method for performing comparison of two signals

Abstract: A comparator and a method for comparing one digital signal composed of n bits to a second digital signal also composed of n bits. The comparator includes a predetermined number of logic levels. The comparator samples and compares selected bits of the two signals in any order and applies Boolean algebra operations to the signals without reference to any comparison of any other bits of the signals. The comparator provides an output signal of one logic level if one signal is greater than the other, and of a second logic level if the one signal is less than or equal to the other signal.

Fault alignment control system and circuits

Abstract: This permutation circuit can be considered to be a multibit adder without a carry. In one embodiment it takes the form of m address bits being fed to m+y 2-way exclusive OR gates (12) with m+y permutation bits to generate m+y input bits accessing a decoder (10) with 2m output positions. In another embodimentthe decoder takes the form of an m-bit adder (14) which adds m address bits to m permutation bits to generate an m-bit actual address. Multiple decoders of both types may be joinedtogether in various combinationsto generate higher order addresses. Also, k full-adders of less than m bits can be used in similar fashion as m+y Exor gates to provide shift rotate capability within a desired block of 2Y rows.

Method of encoding a stream of data bits, arrangement for performing the method and arrangement for decoding the stream of channel bits obtained in accordance with this method

Abstract: Method of connecting a stream of data bits of a binary source signal into a stream of data bits of a binary channel signal. The data bit stream of the source signal is divided into a sequence of five authorized source words of variable lengths. Each of these five authorized source words are converted into a channel word having twice the number of data bits. This conversion has been chosen such that a very small error propagation is obtained and that at the same time very simple electronics are required. For dividing the data bit stream into information blocks and for providing the timing during the decoding operation a very suitable synchronizing word is used.

Distortion analyzer for quadrature demodulated data

Abstract: Method and apparatus for displaying measures of distortion present at the outputs of a quadrature demodulator. From each of the in-phase and quadrature channels of the demodulator there are acquired n parallel bits, m of these bits being the demodulator data output of the associated channel and (n-m) bits being error bits for the channel. The n bits for each channel are converted to a signal acceptable to a plot display device and applied to orthogonal axes of the device. In addition, an absolute value of the (n-m) error bits for each channel is derived. This absolute value is filtered and displayed, as by a meter, for each channel.

Ratio comparator for digital signals

Abstract: In a system for comparing the ratio of two numbers to a threshold, the bits of each number are compared in groups comprising less than the total number of bits. The most significant group of bits are first compared, and if they contain sufficient information to make the comparison, the result thereof is indicated. If the most significant group of bits does not contain sufficient information, the comparison is made based upon the next higher order group of bits that does contain sufficient information. In some situations, it is desirable to obtain information about the next lower order group of bits in order to verify whether a determination is correct. Each of these situations has a unique address in a memory unit dedicated to the next lower order group of bits. In response to an input signal indicating that a determination subject to verification has been made, this memory unit provides an output signal that indicates the validity of the determination, based upon input information to this memory unit that is not contained in the higher order group of bits.

Logic for calculating bit error rate in a data communication system

Abstract: A system for determining the bit error rate in a communication system comprising logic for generating a stream of data bits, bit extracting logic for periodically extracting N consecutive bits after the occurrence of every Mth bit, where the N consecutive bits are divided into a group of A bits and a group of C bits, where A and C are equal integers, and a single B bit is positioned between the group of A and C bits, where M>>A, where the N bits can be any combination of binary 1's and 0's. Logic extracts and stores a finely quantized sample of the B bit of each group of N bits. An adder adds an auxiliary group of X bits to the N bits to form a memory address consisting of A, B, C, and X bits. A plurality of memories each has storage locations for a single finely quantized B bit sample. Each memory further is selectable by a unique combination of the binary bits A+B+C with any given storage location in each memory being accessible by various combinations of the X bits. Appropriate logic by a predetermined algorithm calculates the current probability of bit rate error.

The Use of a High-Speed 12-Bit A/D Converter for Digital Sampling of Communication Signal Carriers

Abstract: : The use of an A/D converter is considered for digital sampling of modulated waveforms obtained from an antenna Demodulation is assumed to occur following the digital sampling process, either by using a high speed digital processor or by using a more conventional receiver following reconstruction of the analog waveform by a D/A converter Since many communication carriers are not conditioned for jam-resistance by coding and spectrum-spreading techniques, a large instantaneous linear dynamic range is necessary to permit the detection and modulation of a small desired signal in the presence of a strong inband interfering signal Consequently, our interest lies in A/D converters having a large number of quantization bits - a condition that is necessary for large linear dynamic range The effects of A/D device parameters such as quantization resolution (number of bits), sampling rate, and aperture uncertainty are discussed A 12-bit A/D converter having an aperture uncertainty of 25 psec and a maximum sampling rate of 5 MHz was used to experimentally determine the magnitude of the spurious-free dynamic range that could be obtained with present off-the-shelf technology A larger number of quantization bits would have resulted in unacceptably slow speed and an unacceptably low maximum frequency limitation A smaller number of bits would have yielded a smaller spurious-free dynamic range Since we did not have a digital processing facility to analyze the A/D directly, a D/A converter, deglitcher (sample-and-hold), and a high quality spectrum analyzer were used to evaluate the A/D performance Consequently, the results reported are characteristic of the composite A/D-D/A- deglitcher system rather than the A/D alone