Showing papers on "Fault coverage published in 1977"

Test generation for large logic networks

Abstract: A system for automatic test pattern generation for large logic networks is described. The network to be tested is assumed to comply with a set of ground rules for testability. The system includes features for automatic subdivision of the network into easily tested sub-networks, automatic test generation programs, and a post-processor which produces a highly efficient test program. Applications to fault diagnosis, and to fast processing of design changes and variations for machine features are considered.

Simulator-oriented fault test generator

Abstract: The problem of generating tests for sequential logic networks has become severe with large-scale integration (LSI). Since the internal gates cannot be tested by direct measurements, it is imperative that a rigorous logic test be developed to ensure quality at the chip level. The sequential complexity of many LSI chips exceeds the practical limitations of the familiar technique of modeling sequential logic for the application of combinational logic test-generation algorithms. Although other approaches, such as pseudo-random pattern generation, have been tried with some success, the pattern count may be quite large. This paper describes a method of test pattern generation that was developed with three objectives: to generate long pattern sequences systematically when needed, to model the sequential logic accurately so that any test generated would be valid, and to focus on assumed faults such as stuck 1 and stuck 0. Also discussed are the strengths and limitations of this method and some comparative results.

SCIRTSS: A Search System for Sequential Circuit Test Sequences

Abstract: This paper describes SCIRTSS (a sequential circuit test search system). An analytical basis is given for using tree search techniques in determining test sequences for sequential circuits. The basic algorithm for the system of SCIRTSS programs is described and the extent to which the user can influence the search procedure is discussed. Included are the results of the application of SCIRTSS to eight sequential circuits of varying complexity on each one of which it succeeded in finding a fault detection sequence for at least 98 percent of the simple logical faults. This suggests that SCIRTSS can be effective on more complex LSI parts than other automatic test generation methods currently available. Breaking the tree search into two separate search procedures and partitioning circuits when possible into control and data sections are unique features which contribute to SCIRTSS efficiency.

An efficient method of fault simulation for digital circuits modeled from boolean gates and memories

Abstract: The ability to predict the behavior of digital circuits containing faults is required for the verification and automatic generation of fault detection tests, and for the creation of fault dictionaries. The most common method of prediction is with a fault simulation program.Fault simulators simulate the fault-free (good) circuit and each of the possible faulty circuits. In most cases, the faulty circuit is assumed to contain only a single fault modeled as either a component input or output stuck-at-0 (SA0) or stuck-at-1 (SA1). Even so, a typical circuit may imply hundreds to thousands of possible faulty circuits. Reducing the cost of simulating large numbers of faulty circuits is the first major consideration in fault simulation.

Special Feature: Fault Diagnosis of Microprocessor Systems

Abstract: The rapid growth in numbers of microprocessor-based intelligent terminals—e.g., POS terminals, communication preprocessors, and I/O processors for large computer systems—has brought with it increased awareness of the importance of guaranteeing the correct operation of the microprocessor without disturbing the use of the system. This in turn has focused attention on fault detection, location, and repair in such systems.

Fault Diagnosis of Semiconductor Random Access Memories.

Abstract: : This report deals with the problems of testing semiconductor random access memories and of locating faults on a memory board. Memory test procedures can be divided into three classes, functional testing, pattern sensitivity testing and DC parametric testing. Existing test procedures for testing semiconductor memories are either limited in their fault coverage or require a prohibitive amount of time. A new functional test procedure based on a fault model that takes into account a large variety of faults encountered with semiconductor memories is presented. The fault model is not based on the 'gate' level as in classical fault diagnosis but is formulated on a higher level in terms of functional blocks, like the decoder and the memory cell array. The proposed functional test procedure takes 0(n x log sub 2) units of time where n is the number of words in memory. This gives a dramatic improvement in the testing time required over well-known test procedures line 'galpat' and 'Walking Ones' which take 0(n squared) units of time. Algorithms for the functional test procedure are given. The problem of locating faults on a memory board to memory chips, decoder logic, data registers, and bussing structure is discussed. A test scheme for this problem is given. Finally various test procedures presented in the thesis are evaluated for fault coverage, time requirement and east of implementation.

Maintenance strategies for PCM circuit switching

Abstract: During all the system design phase of an SPC switching system, a considerable effort is devoted to maintenance, both from a hardware and software point of view. The maintenance phases include fault detection, fault analysis (e.g., identification of the faulty security block within the switching system), fault isolation, fault reporting, fault localization, fault clearance, and restoration to service with the eventual requalification and reinitialization of the repaired security block. The paper mainly discusses fault detection and fault analysis strategies with specific reference to PCM digital switching systems. Different means leading to fault detection are presented with reference to central control, network access devices (scanners, drivers, markers), and digital switching network (duplicated or not duplicated). These means include automatic on-line tests (monitoring and routining), on-demand on-line tests, and alarm handling. Fault analysis can be accomplished by means of a deductive or a statistical method. As the latter seems more attractive, three basic methods of statistical fault analysis are presented. They use, respectively, two counters (operation and fault counter) per security block; one fault counter per security block; one "historical" fault stack, in which all the identities of security blocks involved in faulty operations are stored. The above fault analysis strategies are compared mainly in terms of core memory occupancy, processor time, and software complexity.

Maintenance Strategies for PCM Circuit Switching

Abstract: During all the system design phase of an SPC switching system, a considerable effort is devoted to maintenance, both from a hardware and software point of view. The maintenance phases mdude fault detection, fault analysis (eg., identification of the faulty security Mock within the switching system), fault isohtion, fault reporthg, fault localization, fault clearance, and restoration to with the eventual reqdificabion and reinitializa- tion of the repaired security Mock. The paper mainly discusses fault detection and fault analysis strategies with specific reference to F" digital switching systems. Different means leading to fault detection are. presented with refer- ence to central control, network access devices (scanners, drivers, markers), and digital switching network (duplicated or not duplicated). These means include automatic on-line tests (monitoring and routin- in&, on-demand on-line tests, and alvm handling. Fault analysis can be accomplished by means of a deductive or a statistical method. As the latter seems more attractive, three basic methods of statistical fault analysis are presented. They use, respec- tively,

Modelling techniques for dynamic logic and test pattern generation of a microprocessor

Abstract: Most of the software logic simulators available today have been designed with particular application to the simulation of static logic. Dynamic logic, using transmission gates, a bidirectional analog device, has, however, become popular in MOS LSI due to the higher levels of integration it allows. A modelling technique has been developed by which an interconnection of transmission gates can be simulated on simulators designed for static logic. The model preserves the fault-free behavior as well as the faulty behavior of the original circuit. Preservation of the latter property is particularly important in simulators having fault injection capabilities.The modelling technique was used for doing the fault simulation and test pattern generation of a single dynamic microprocessor. During this process, it was observed that a very high level of fault coverage can be obtained in that portion of the microprocessor which contains the different registers and the arithmatic logic unit. However, failures in the decoder which decodes the contents of the instruction register are more difficult to detect and the microprocessor has to be exercised through complicated sequences to detect them.