Showing papers on "Fault indicator published in 1977"

Fast generator protection against internal asymmetrical faults

Abstract: An on-line digital computer technique for the protection of a generator against internal asymmetrical faults is described in this paper. The proposed technique relies on the detection of a second harmonic component in the field current at the onset of a fault in the armature winding. Discrimination against external faults is achieved by monitoring the direction of the negative sequence power flow at the machine terminals. Tests have been conducted on a laboratory synchronous generator for various types of internal and external faults. Results show that the total time for internal fault detection and tripping is well within half a cycle of the 60 Hz signal. A simple extension to negative sequence relaying and loss of excitation relaying is proposed.

Ground fault protective systems with predetection neutralization of reactive currents

Abstract: Ground fault protective systems are disclosed in which fault signals are generated in response to differential currents carried by electrical supply lines. A circuit breaker interrupts power on the supply lines when the fault signals exceed a given magnitude and duration. Downstream reactances to ground from one or more supply lines give rise to spurious fault signals which do not characterize true ground fault conditions. These spurious fault signals are cancelled prior to detection by means of neutralizing auxiliary circuits. The resulting fault signals exhibit a high signal-to-noise ratio.

Fault trees for diagnosis of system fault conditions

Abstract: Methods for generating repair checklists on the basis of fault tree logic and probabilistic importance are presented. A one-step-ahead optimization procedure, based on the concept of component criticality, minimizing the expected time to diagnose system failure is outlined. Options available to the operator of a nuclear power plant when system fault conditions occur are addressed. A low-pressure emergency core cooling injection system, a standby safeguard system of a pressurized water reactor power plant, is chosen as an example illustrating the methods presented.

Fault tolerant 92160 bit multiphase CCD memory

Abstract: technique in combination with laser burned fuses. During chip test, good and bad blocks are identified and the bad blocks are disconnected from the power supply by laser burned fuses. Each good block has its shorted address line fuse burned out which puts it in series with the othcr good blocks; Figure 2. No special masks are required. The good blocks are linked together by a serial addressing technique. In effect, thc linked blocks can be thought of as bit positions in a shift register such that if a “1” is inserted into the register, it can be shifted thru the register (blocks). Thus, to address a block, the “1” is shifted to the desired block and a common enable line is then activated. Data can then be written or read from the addressed block. Thus, at the system level, it is only necessary to guarantee a certain total number of good blocks to span the address range. No special method of block identification or bookkeeping of parts is required; this simplifies use.

Ground fault receptacle

Abstract: An electric receptacle for trade size outlet boxes having a ground fault circuit interrupting machanism incorporated therein. A receptacle housing includes contact jaws seated therein to receive the plug of a conductor leading to a load, electronic components to detect a ground fault and grounded neutral condition on the load side of the receptacle, plus a coil and trip mechanism to open the receptacle circuit on occurrence of a ground fault or grounded neutral condition. The complete receptacle assembly is approximately the same depth as conventional household receptacles which do not have ground fault circuit interrupting means included therein. Means to periodically test the ground fault interrupting mechanism is also included in the receptacle assembly, as well as means to indicate the circuit has been interrupted and means to reset.

An efficient method of fault simulation for digital circuits modeled from boolean gates and memories

Abstract: The ability to predict the behavior of digital circuits containing faults is required for the verification and automatic generation of fault detection tests, and for the creation of fault dictionaries. The most common method of prediction is with a fault simulation program.Fault simulators simulate the fault-free (good) circuit and each of the possible faulty circuits. In most cases, the faulty circuit is assumed to contain only a single fault modeled as either a component input or output stuck-at-0 (SA0) or stuck-at-1 (SA1). Even so, a typical circuit may imply hundreds to thousands of possible faulty circuits. Reducing the cost of simulating large numbers of faulty circuits is the first major consideration in fault simulation.

Ground fault protection system for multiple source distribution networks

Abstract: Various embodiments of a ground fault protection system are disclosed for protecting a multiple source distribution network consisting of at least two sources having their neutral points interconnected by main neutral and tie neutral bus and also typically by separate ground connections. The system operates to selectively trip a ground fault circuit interrupter by distinguishing between normal neutral loading regardless of the routes taken by neutral currents in returning to the sources and a ground fault regardless of the routes taken by ground fault currents in returning to the source feeding the fault.

Maintenance strategies for PCM circuit switching

Abstract: During all the system design phase of an SPC switching system, a considerable effort is devoted to maintenance, both from a hardware and software point of view. The maintenance phases include fault detection, fault analysis (e.g., identification of the faulty security block within the switching system), fault isolation, fault reporting, fault localization, fault clearance, and restoration to service with the eventual requalification and reinitialization of the repaired security block. The paper mainly discusses fault detection and fault analysis strategies with specific reference to PCM digital switching systems. Different means leading to fault detection are presented with reference to central control, network access devices (scanners, drivers, markers), and digital switching network (duplicated or not duplicated). These means include automatic on-line tests (monitoring and routining), on-demand on-line tests, and alarm handling. Fault analysis can be accomplished by means of a deductive or a statistical method. As the latter seems more attractive, three basic methods of statistical fault analysis are presented. They use, respectively, two counters (operation and fault counter) per security block; one fault counter per security block; one "historical" fault stack, in which all the identities of security blocks involved in faulty operations are stored. The above fault analysis strategies are compared mainly in terms of core memory occupancy, processor time, and software complexity.

Fault indicator including a reed relay responsive to above normal current flow in a conductor

Abstract: A fault indicator includes a reed relay disposed for responding to a magnetic field surrounding a conductor particularly when conducting above-normal current. The relay triggers a latch which enables a counter and starts a pulse generator which, in turn, drives a flasher, and the pulses are counted for resetting the device by resetting the latch after a number of pulses have been counted. The reed relay is disposed in a position for adjustment of alignment and misalignment in relation to the conductor.

Programmable fault detecting relay for a transformer

Abstract: A programmable fault detecting relay for fluid cooled electrical apparatus utilizes a pressure transducer to provide an electrical input to an electronic discriminating circuit. The circuit discriminates between through fault pressures and internal fault pressures and provides an output upon the occurrence of an internal pressure fault.

Fault indicator for distribution line

Abstract: PURPOSE:To make fault indication lamps for substantially one distribution line enable to indicate faults on a plurality of distribution lines.

Minimal Fault Tests for Redundant Combinational Networks

Abstract: This correspondence is concerned with the detection of permanent faults in redundant combinational networks. Fault masking in such networks is examined. A method for determining an optimal test set that will detect all detectable faults is given.

Statistical Characterization Of Intermittent Faults In Digital Systems

Abstract: SmMARY In this paper, the problem of characterizing the stochastic behavior of intermittent faults is considered. Three analytical models for intermittent faults in digital systems are discussed. First model assumes that the intermittent faults can be modeled as a renewal process. The second model is a finite-state Narkovmodel. Finally, in the third model the fault-free interval between two intermittent faults is considered and the intermittent fault process is characterized in terms of these fault-free i ntervals. It is expected that these models will find a pplication in the prediction of performance of detection procedures for intermittent faults.

Maintenance Strategies for PCM Circuit Switching

Abstract: During all the system design phase of an SPC switching system, a considerable effort is devoted to maintenance, both from a hardware and software point of view. The maintenance phases mdude fault detection, fault analysis (eg., identification of the faulty security Mock within the switching system), fault isohtion, fault reporthg, fault localization, fault clearance, and restoration to with the eventual reqdificabion and reinitializa- tion of the repaired security Mock. The paper mainly discusses fault detection and fault analysis strategies with specific reference to F" digital switching systems. Different means leading to fault detection are. presented with refer- ence to central control, network access devices (scanners, drivers, markers), and digital switching network (duplicated or not duplicated). These means include automatic on-line tests (monitoring and routin- in&, on-demand on-line tests, and alvm handling. Fault analysis can be accomplished by means of a deductive or a statistical method. As the latter seems more attractive, three basic methods of statistical fault analysis are presented. They use, respec- tively,

Power system short circuit planning for superconducting power transmission

Abstract: Short circuit capacity of large power generation facilities is limited by the internal reactance of the generator and the impedance of connecting bus work and transformers. In the event of a fault on a generator get away circuit, d-c offset could double the short circuit current on the cable for a period of from 3 to 5 cycles after the fault initiation. High performance circuit breakers (PCBs) can shorten this fault duty time to 1 cycle (17 msec). If a superconducting cable is arbitrarily designed for 10X rated current fault withstand, its capital and operating cost may be dramatically increased. What can be done? First, a careful look at generator step up transformers and circuit breaker capability shows a marked tendency for this equipment to have very high costs if the generator bus connection scheme is planned to allow very large fault currents. However, the power system designer can set up the circuit arrangement so that massive fault currents are avoided. Second, the development of fault current limiting devices promises the possibility of holding fault current levels below 2X or 3X rated current. DC superconducting cables do not require this extra fault duty consideration, because the rectifier inverter system protects them. Usual fault conditions on d-c cable are such that less than 2X rated current will occur on the cable during a fault. Because a-c superconducting cables include very high fault current capability in their design, a careful trade-off study with current limiters, generator bus layout alternatives and possible d-c cable application should be done to assure that the final design may more readily achieve reasonable economics.