Showing papers on "Flip-flop published in 1976"

De-glitchable non-metastable flip-flop circuit

Abstract: Title of the Invention DE-GLITCHABLE NON-METASTABLE FLIP-FLOP CIRCUIT Abstract of the Disclosure The flip-flop circuit of the present invention is one that cannot glitch or enter a metastable hang-up state and has a probability of one of being completely settled at some given finite time following clocking. The flip-flop circuit is com-prised of an input logic gate, an integrator and a logic latch circuit. In operation, the input logic gate changes state upon the coincidence of input signals,which change in state causes the integrator to change output level at a controlled rate. The latch circuit is sensitive to the output level of the integrator and changes state only when the integrator's output level reaches or exceeds preselected thresholds.

Analog-to-digital converter

Abstract: A single channel analog-to-digital converter of the pulse density code type includes a D-type flip flop, a clock source to clock the flip flop, an analog signal input coupled to the D input of the flip flop and at least one feedback circuit connected from the Q output of the flip flop to the D input of the flip flop. The feedback circuit includes a means to integrate the Q output signal of the flip flop.

Bistable semiconductor flip-flop having a high resistance feedback

Abstract: A CMOS bistable semiconductor flip-flop circuit having a storage element formed by a first and a second inverter. The output of the second inverter is directly connected to the input of the first inverter. The first inverter output is coupled to the second inverter input through a high resistance feedback of resistance value which is substantially high with respect to the low output impedance of the first inverter. A charge storage device and gates alternately store the state of the storage element and thereafter provide the stored signal to the second inverter input. Additionally, a device is connected to the input of the second inverter to provide a reset or set function.

Hazard-free clocked master/slave flip-flop

Abstract: The clocked flip-flop circuit of the present invention is one that cannot be caused to yield an erroneous output upon a skew in a clock pulse or, equivalently, the offset of such pulse with respect to its complement. The disclosed flip-flop circuit is comprised of a J-K master portion and a D latch slave portion. Each portion includes a gate having no operative functional definition as respects provision of an output under normal operating conditions of the circuit. In normal operation, the circuit, exclusive of the additional gates, provides HOLD, SET/RESET and TOGGLE functions according as the setting of J and K inputs. Upon skew of a clock pulse, the additionally provided gates insure integrity of the outputs corresponding to the J and K settings by defining a failure mode of operation of the flip-flop, independent of the clock.

Injection logic arrangements

Abstract: A logic flip flop arrangement wherein each of the two outputs of the flip flop has an output gate associated therewith, wherein an input of each of the output gates is connected to an output of a driving gate, and wherein at least one of the output gates has an output thereof combined with an output of that one of the driving gates which is associated with the other output gate to provide a logic function.

Flip-flop with false triggering prevention circuit

Abstract: A set-reset flip-flop is taught utilizing NAND gate logic elements and an internally connected resistor-capacitor circuit. The time constant of the resistor-capacitor network is such that valid triggering pulses for the input terminal of the flip-flop will not be propagated through the flip-flop to change the output state thereof unless the pulses are of a minimum duration. The duration of such pulses are chosen to be significantly larger than the duration of expected random noise which may appear on the input terminal of the flip-flop. Such being the case, noise signals are not propagated through the flip-flop to change the state thereof. A discharge network is provided for the capacitor to quickly discharge the capacitor at the termination of each input pulse, whether noise or triggering, so that an accummulaton of noise pulses will not cause a shift in the output of the flip-flop.

Dynamic IGFET delay flip-flop as shift-register element - has three gates each with three or four p-channel and n-channel IGFETs

Abstract: The dynamic IGFET delay flip-flop (as an element in a shift register) consists of three gates (A, B, C) each containing three or four IGFETs. The control signals (e.g. clock pules) are applied to the gates of the input stage's IGFETs. The first two IGFETs in this stage are p-channel and the third (T3) is an n-channel type. The second stage (B) has four IGFETs: two p-channel, and two n-channel. One pair of gates in this stage are connected to the clock signal and the other pair to the first stage's output. The third stage (C) consists of one P-channel and two N-channel IGFETs. This stage has the gate of one of its n-channel IGFETs coupled to the clock signal and the other two gates to the second stage's output.

Regenerative circuit of flip-flop type - regenerates signal for charge coupled devices

Abstract: CCD (3, 5) output is connected to the flip-flop (1) circuit point (11), CCD input, into which the regenerated signal is to be applied, is connected, depending on the required phase, either to the point (11) of the same circuit branch (13, 16) or to the circuit point (12) in the other branch (14, 17). The flip flop circuit consists essentially of two switching transistors (13, 14) and two load transistors (16, 17). Cross connections (18, 19) create a flip-flop circuit from the four transistors. The load transistors have gate connections which can be applied to a divided pulse voltage. The complete flip-flop lays between terminals (21, 22) which can be connected to a supply voltage.

Storage circuit for electronic emergency-call branch exchange - has clock signal sent via delay line to flip flop

Abstract: The store circuit, for an electronic emergency-call branch exchange, stores the last two keying operations of the attendant operator and also their sequence. A clock signal is sent via a delay line (311) to a flip flop (312) to allow the information about keying to be accepted by a store (32, 33). The clock signal is applied to the set input of the flip flop (312) and is generated by a binary coder (30) that converts the operated key's signals. The output from the flip flop is differentiated by two differentiating units (313, 314), and the differentiated output is used to free a store (32, 33) for accepting the binary signals from the coder (30).

Frequency comparator operating as band-pass filter - consists of two monoflops storage flip-flop and logic cct.

Abstract: The two monoflops are so linked by the logic circuit together and with the resetting or setting input of the storage flip-flop, that, when both monoflops are in their stable positions, the logic circuit generates a level which holds the storage flip-flop in a certain position. The first monoflop is triggered by an edge of the input signal, and the edge produced at the end of this flip-flop metastable state triggers the second monoflop whose pulse is applied in the signal input of the storage flip-flop to whose clock pulse input the input signal is applied.

Parity detection circuit for programmable logic systems - has multiple inputs and outputs with control memory buffer store and flip-flop

Abstract: A coefficient register is connected to a programmable control memory and through a buffer store to a flip-flop, an accumulator, up-down counter and a parity detector. A parity generator is connected to the input/output circuits and associated parity registers. a micro programmer controlled by a clock generator via a counter provides sequential control pulses for the rest of the circuit. Reference signals from the input/output circuits feed a parity generator whose output is connected with that of input/output registers. A comparator connected to the accumulator and address gives a control pulse to modify the contents of the parity registers.