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Showing papers on "Gate driver published in 1970"


Patent
Uryon S Davidsohn1
07 Dec 1970
TL;DR: In this article, diffusion guarding of the gate electrode of a MOSFET device and utilizing the drain of one MOSFLT device as the source of the next integrally formed MOS FLT device are discussed.
Abstract: Metal-oxide-silicon field effect transistors (MOSFET) are shown utilizing diffusion guarding of the gate electrode of a MOSFET device and utilizing the drain of one MOSFET device as the source of the next integrally formed MOSFET device. Other types of isolation shown include the surrounding of a functional unit with a source diffusion area, and/or permanently connecting a gate electrode to a potential level for preventing signal flow past such a gate.

26 citations


Patent
28 Aug 1970
TL;DR: In this paper, a voltage boosting circuit provides a boosted voltage level on the gate electrode of a field effect transistor driver in response to a logic input signal during a second phase of a four phase clock cycle.
Abstract: A voltage boosting circuit provides a boosted voltage level on the gate electrode of a field effect transistor driver in response to a logic input signal during a second phase of a four phase clock cycle. A field effect transistor connected as a rectifying device prevents the gate voltage from changing during at least the third and fourth phases of the clock cycle. As a result, the field effect transistor driver provides a DC output voltage level. During the second phase of the subsequent cycle, if the input has not changed, the gate voltage is reset to the boosted voltage level. If the input has changed, during the first phase of the clock cycle the gate voltage is reset to a different voltage level and maintained until the input again changes.

17 citations


Patent
09 Feb 1970
TL;DR: In this paper, a solid-state integrator that receives tow information signals, namely, a weight signal and a speed signal, integrates these signals and provides an output signal proportional to the product thereof that is indicative of total weight of material that has passed a scale.
Abstract: A solid-state integrator that receives tow information signals, namely, a weight signal and a speed signal, integrates these signals and provides an output signal proportional to the product thereof that is indicative of total weight of material that has passed a scale. The weight signal comes from the scale and is a negative DC voltage having an amplitude proportional to the weight per unit length of conveyor belt. The speed signal comes from a belt rider measuring wheel operated pulse generator and consists of 100 uniform width pulses per foot of belt travel. An amplifier at the integrator input amplifies the weight signal and has an input bias adjusting potentiometer for zero calibration and an attenuation adjusting potentiometer at its output for span calibration. Span refers to the correct total weight of a run of several belt circuits with a test weight. Zero refers to zero total weight of a run of several belt circuits empty. For integration purposes, the speed pulses are shaped, get in step with the clock, and are stretched to desired width by a clock controlled preset pulse width generator. This pulse, called ''''fill'''' pulse, whose width is precisely controlled by the clock, operates an analog gate via a gate driver, allowing DC voltage representing weight on a scale to enter the integrator and charge the integrating capacitor therein. The integrator is bidirectional and will accumulate both positive and negative charges and will provide a DC voltage having a polarity and amplitude proportional to the algebraic sum thereof. The integrator receives two control signals, namely, a fill pulse described previously and ''''dipout'''' pulses, the latter being essential in an integration process -- without them the integrator would saturate. Dipout pulses can be in step with the clock pulse, or in step with the inverted clock pulse, depending on demand. The dipout pulses operate the other analog gate via a gate driver which allows the positive or negative half-cycles of the sine wave voltage to discharge the integrator capacitor. Dipout is started by a voltage level detector so that the integrator does not exceed its capacity in continuous running. The uniform dipout quantities are counted in a forward-backward operable weight totalizer to provide a running indication of the total weight of material that has passed over the scale and for other control and indication purposes. This method of integration -- where the sine wave drives the transducer, generates clock and inverted clock pulses, controls the pulse width of the fill pulse and the pulse width of the dipout pulse, and the same sine wave is used for dipping out the integrator -- all this provides ''''bridging action,'''' that is, automatic self-compensation in response to frequency or amplitude variation in the sine wave voltage so that no error will be introduced in the output.

13 citations


Patent
22 Jun 1970
TL;DR: Driver circuitry for sensing the direction of bias across controlled switching devices such as silicon controlled rectifiers and providing sufficient gate drive therethrough when the device is forward biased and removing the gate drive when reverse biased as discussed by the authors.
Abstract: Driver circuitry for sensing the direction of bias across controlled switching devices such as silicon controlled rectifiers and providing sufficient gate drive therethrough when the device is forward biased and removing the gate drive when reverse biased.

3 citations


Patent
08 Sep 1970

Patent
Arden J Wolterman1
17 Nov 1970