Showing papers on "Gate driver published in 1979"

Compensated dual injector driver

Abstract: A compensated dual injector driver circuit for controlling the current to either of a pair of electromagnetic solenoid fuel injectors is disclosed. The driver circuit includes a pair of analog bilateral switches operably connected to the control terminals of two driver transistors whose power terminals are coupled serially with the coils of the injector solenoids. A driver amplifier generating a current control signal for the driver transistors is connected to a common input of the two switches. Either of the switches is selected for closure by a logical input from a select line thereby choosing the individual injector to be energized. The driver amplifier in response to the leading edge of a control pulse regulates the conductance of the selected transistor with the current control signal to initially draw current through the injector coil until it reaches a peak value. At the time the peak current is attained, the driver amplifier then switches the control current to a holding value. The peak and the holding current levels are measured by a negative feedback loop from a sense resistor commonly connected in series with each set of coils and driver transistors to indicate the magnitude of current therethrough. The circuit further includes a means for controllably collapsing the magnetic field stored in the injector coils when the injector driver transistors are turned off in response to the trailing edge of the control pulse. Compensation is provided to the driver amplifier for altering the hold level current in accordance with variations in the battery voltage. The differing levels of hold current with changing battery voltage will modify the closing time of the injector oppositely to those changes produced in the opening times by the battery voltage.

Gate circuit for gate turn-off thyristor

Abstract: A gate circuit for gate turn-off thyristors is disclosed which includes a turn-on circuit formed of a series combination of a turn-on power source and an NPN transistor and a turn-off circuit formed of a series combination of a turn-off power source and a thyristor, and in which a PNP transistor is provided between the anode and gate of the thyristor in such a manner that the base of the NPN transistor and the base of the PNP transistor are connected to each other and a junction of these bases receives a control signal for turning on or off a gate turn-off thyristor.

Floating gate amplifier using conductive coupling for charge coupled devices

Abstract: A floating gate amplifier in a charge-coupled device (CCD) permitting non-destructive readout, where the floating gate is conductively coupled through a high resistance element to a bias voltage. The floating gate is defined by a lower level of metallization which is embedded in an insulating layer and crosses the charge transfer channel. In one embodiment the floating gate is connected to the source of a metal-oxide-semiconductor transistor and the drain of the transistor is connected to an upper level conductor which is a bias line. In another embodiment, the anode of a diode is connected to the floating gate and the diode cathode is connected to the bias line. A pair of control gates adjacent to and partially overlapping the floating gate transfer charge packets and improve sensitivity. Reading is accomplished by detecting voltages induced on the floating gate by the charge packets.

Inverse floating gate semiconductor devices

Abstract: INVERSE FLOATING GATE SEMICONDUCTOR DEVICES Abstract of the Disclosure An MOS stacked gate structure for an EPROM has an upper floating gate and a lower selection gate permitting shorter erasal time, lower selection gate voltage and a compact EPROM structure. - i -