Showing papers on "Logarithmic number system published in 2002"

Automatic floating-point to fixed-point conversion for DSP code generation

Abstract: The development of methodologies for the automatic implementation of floating-point algorithms in fixed-point architectures is required for the minimization of cost, power consumption and time to market of digital signal processing applications. In this paper, a new methodology of implementation in Digital Signal Processors (DSP) under accuracy constraint is presented. In comparison with the existing methodologies, the DSP architecture is completely taken into account for optimizing the execution time under accuracy constraint. The justification and the different stages of our methodology are presented.

Logarithmic Number System and Floating-Point Arithmetics on FPGA

Abstract: An introduction to a logarithmic number system (LNS) is presented. Range and precision of this arithmetic is briefly discussed. We show that the LNS arithmetic is suitable for a FPGA implementation. A case study will compare parameters of our LNS arithmetic library to a conventional floating-point arithmetic.

Introduction to digital filters

Abstract: Digital filters operate on digitized analog signals, so the digitization process is important and is critical in the system design This chapter outlines the process of digital filtering Digitization requires the analog signal to be sampled and then converted into a digital value, based on the amplitude of the sample Data sampling and digitization operation are covered before considering digital filters The two types of digital filter: finite impulse response and infinite impulse response are described briefly The functions required to form a digital filter include multipliers, adders, and delays The Digital signal processors (DSPs) are described in terms of how the functions required in a digital filter are built into the construction or can be created in software The type of arithmetic DSPs use to handle data during signal processing is also described The choice of processing device determines whether fixed or floating-point arithmetic is used Fixed-point arithmetic can affect accuracy and stability

A 2-digit multidimensional logarithmic number system filterbank for a digital hearing aid architecture

Abstract: This paper addresses the design and implementation of a filterbank for digital hearing aids using a multi-dimensional logarithmic number system (MDLNS). The logarithmic properties of the MDLNS allow for reduced complexity multiplication, and large dynamic range, and a multiple-digit MDLNS provides a considerable reduction in hardware complexity compared to a conventional logarithmic number system (LNS) approach. In this paper we discuss the design and implementation of both a 1-digit and 2-digit 2-D MDLNS filterbank and provide initial simulation results.

Matrix engine for signal processing applications using the logarithmic number system

Abstract: An architecture design is presented for a device based upon the logarithmic number system (LNS) that is capable of performing general matrix and complex arithmetic, with features useful for DSP system-on-chip applications. A modified LNS addition/subtraction unit is employed in multiple execution units to achieve a maximum single-precision floating-point (FP) equivalent throughput of 3.2 Gflop/s at a clock frequency of 200 MHz. Each execution unit is capable of computing functions of the form (ab + cd)/sup e/ for e /spl isin/ {/spl plusmn/0.5, /spl plusmn/1, /spl plusmn/2} in a 5-stage arithmetic pipeline and returning a result every cycle, yielding a considerable per-cycle improvement over both floating- and fixed-point systems. Comparisons with existing devices and a single floating-point unit are given.

Pipelined implementations of the a Priori Error-Feedback LSL algorithm using logarithmic arithmetic

Abstract: In this paper we present several implementations of the Modified A Priori Error-Feedback LSL (EF-LSL) algorithm [1] on the VIRTEX FPGA. Its computational parallelism and pipelinabilty are important advantages. Internally, the computations are based on the logarithmic number system. We compare 32-bit (SINGLE-ALU or DUAL-ALU version) and 20-bit (QUADRI-ALU versions). We show that the LNS implementation can outperform the standard DSP solutions based on 32-bit floating-point processors.

Optimization of LNS operations for embedded signal processing applications

Abstract: This paper introduces an optimization technique for the design of logarithmic arithmetic-based embedded signal processors. The fundamental concept of the proposed technique is the determination of the optimal values of the logarithmic base b, which minimize the number of memory words required to be stored in look-up tables (LUTs) for the implementation of logarithmic-arithmetic addition and subtraction. The application of the proposed technique is facilitated by an introduced formula, which returns the optimal bases using the equivalent linear word length n as a parameter. Optimal values of b are identified for the cases b 1 and their performance is compared. The comparison reveals that the absolute minimum of memory words is achieved by selecting particular values of b, b<1. The proposed technique exploits recently introduced equivalence criteria between linear and logarithmic number representations and it is shown to reduce up to two times the size of the required memory LUT when compared to the conventional choice b=2, without imposing any overhead on the logarithmic architecture.

Efficient conversion from binary to multi-digit multi-dimensional logarithmic number systems using arrays of range addressable look-up tables

Abstract: The multi-dimensional logarithmic number system (MDLNS), with similar properties to the logarithmic number system (LNS), provides more degrees of freedom than the LNS by virtue of having two orthogonal bases and the ability to use multiple digits. Unlike the LNS, there is no direct functional relationship between binary/floating point representation and the MDLNS representation. Traditionally look-up tables (LUTs) were used to move from the binary domain to the MDLNS domain. This method can be unrealistic for hardware implementation when large binary ranges or multiple digits are used. This paper introduces a range addressable technique for table look-up arrays that allows efficient conversion from binary to single or multi-digit MDLNS.

Digital filtering using the multidimensional logarithmic number system

Abstract: We introduce the use of multidimensional logarithmic number system (MDLNS) as a generalization of the classical 1-D logarithmic number system (LNS) and analyze its use in DSP applications. The major drawback of the LNS is the requirement to use very large ROM arrays in implementing the additions and subtraction and it limits its use to low-precision applications. MDLNS allows exponential reduction of the size of the ROMs used without affecting the speed of the computational process; moreover, the calculations over different bases and digits are completely independent, which makes this particular representation perfectly suitable for massively parallel DSP architectures. The use of more than one base has at least two extra advantages. Firstly, the proposed architecture allows us to obtain the final result straightforwardly in binary form, thus, there is no need of the exponential amplifier, used in the known LNS architectures. Secondly, the second base can be optimized in accordance to the specific digital filter characteristics. This leads to dramatic reduction of the exponents used and, consequently, to large area savings. We offer many examples showing the computational advantages of the proposed approach.

Digital base-10 logarithm converter

Abstract: A circuit ( 100 ) for performing base 10 logarithmic calculations of a binary signal in a digital system that optimizes accuracy of the calculation The circuit comprises a priority encoder ( 108 ) for determining a most significant bit position of the binary number, with the most significant bit representing a base 2 logarithmic integer component of the input binary signal A decimal selector ( 120 ) selects a predetermined number of bits to follow the base 2 logarithmic integer component determined by the priority encoder, with the predetermined number of bits representing a base 2 logarithmic fractional component following the integer component of the input binary signal An adder ( 116 ) combines the integer component with the fractional component to thereby output a base 2 logarithmic value of the input binary signal A multiplier ( 132 ) divides the base 2 logarithmic value of the input binary signal by a base 2 logarithmic value of 10 to thereby output a base 10 logarithmic value of the input binary signal

Matrix based signal processing on a reconfigurable hardware accelerator

Abstract: In this paper we describe a novel architecture for high speed signal processing applications. The respective hardware accelerator is designed to support a certain class of algorithms. The chosen class is based on a special kind of matrix transformation that could be efficiently implemented in terms of CORDIC modules. A consistent notation is presented to ease the process of mapping signal processing algorithms to the considered hardware. It is also shown how to implement complex valued arithmetic with less growth of complexity compared to standard techniques. Some algorithms are examined to illustrate the potential of our approach.

The use of reduced two's-complement representation in low-power DSP design

Abstract: Two's complement signal representation is widely used in the implementation of arithmetic operations. However, it is well-known that its sign-extension can cause undesirable signal transitions in the MSBs of a data-path circuit. We propose a novel technique to reduce the signal transitions due to sign-extension while retaining the simplicity of the two's complement arithmetic operations. The key idea is to generate a signal representation dynamically according to the signal magnitude. This paper discusses the implementation techniques of using reduced representation in data-path designs. We have applied our proposed techniques in several design examples and our experimental results have shown 13% to 32% power reductions.

LNS for low-power MPEG decoding

Abstract: Floating-point and fixed-point are expensive for portable multimedia devices. Low-cost Logarithmic Number System (LNS) arithmetic can reduce power consumption of MPEG decoding in exchange for barely perceptible video artifacts. Different number representations need different word sizes to produce the same quality image. LNS can produce good visual results using fewer bits than fixed point. Rounding to the nearest is often done with fixed point and floating point, but LNS allows a cheaper unrestricted-faithful-rounding mode that does not degrade the visual quality of MPEG outputs. This paper also describes how the Berkeley MPEG tools were modified to carry out these MPEG arithmetic experiments.

Analysis of the LNS implementation of the fast affine projection algorithms

Abstract: It has been shown that a 32-bit logarithmic arithmetic unit can operate faster than, and maintain the accuracy of, a 32-bit floating point unit. It uses the logarithmic number system (LNS), in which a real number is represented as a fixed- point logarithm. In this paper we investigate the implementation of three fast affine projection (FAP) algorithms using LNS. We propose a simplified Conjugate Gradient FAP (SCGFAP) algorithm. We show that the 32-bit or 20-bit LNS implementation of the CGFAP and the SCGFAP algorithm are superior to those of

The application of 2-D logarithms to low-power hearing-aid processors

Abstract: This paper discusses the application of a new two-dimensional logarithmic number system (2DLNS) to the design of low-power processors for hearing-aid applications. The paper concentrates on the architecture of an optimized second base 8-band filterbank and an associated 16-bit binary to 2DLNS converter. The processor takes advantage of the low complexity, orthogonal nature, of the arithmetic used for multiplication and compression, and a simple binary converter. Details are provided for the filterbank processor including the description of a 0.18/spl mu/m CMOS test chip recently submitted for fabrication.

Radar-guided missile programmable digital predetection signal processor

Abstract: A digital predetection signal processor having a main channel processor, a dual path processor and at least two digital filters for filtering digital guidance signals before the signals are input into the main channel and dual processing path processors. The digital filters are each programmable to digitally filter the digital guidance signals to thereby minimize output signal error. The processor further includes a circuit for performing base 10 logarithmic calculations of a binary signal in a digital system for optimizing accuracy of the calculation, and a priority encoder for determining a most significant bit position of the binary number, with the most significant bit representing a base 2 logarithmic integer component of the input binary signal.

Avoiding oddification to simplify MPEG-1 decoding with LNS

Abstract: Low-precision logarithmic number system (LNS) arithmetic can reduce the power consumption for MPEG decoding compared to conventional fixed-point techniques. Although this introduces small numeric errors, which violate the IEEE-1180 standard for the inverse discrete cosine transform (IDCT), the visual effects of such error may be tolerable for portable battery-powered devices, like videophones, that have limited-resolution displays. The MPEG standard achieves video compression by quantization of the data fed to the IDCT. The MPEG decoder must multiply this data by dequantization factors. Such multiplication, by itself, is trivial with LNS since adding logarithms is equivalent to multiplication. The IEEE-1180 standard suggests oddification, where fixed-point data is forced to become odd after dequantization to minimize IDCT mismatch between the encoder and the decoder. Oddification poses an implementation problem for data in LNS format. This paper suggests that the visual effect of LNS without oddification is nearly indistinguishable from LNS with oddification, meaning that the benefits of LNS in MPEG are even greater than previously expected.

A new stable second-order section for recursive digital filters realized with logarithmic arithmetic

Abstract: A new stable second-order digital filter is presented. This filter section enjoys all the stability properties of wave digital filters, including forced-response stability and stability under looped conditions. Conventional stable cascade and parallel realizations of digital filters using logarithmic arithmetic can freely be made by using this second-order section. This substantial advantage is achieved with only a slight extra cost. The simulation results demonstrate that the proposed second-order digital filter implemented with logarithmic arithmetic is always stable under all conditions of operation, as a simple strategy is taken into account in hardware realization.

Audio application implementations on a block-floating-point DSP

Abstract: Hierarchical block-floating-point arithmetic (H-BFP) is applied to a configurable DSP architecture. This new arithmetic has been proposed in order to solve a trade-off problem between complexity and accuracy in implementing conventional block-floating-point arithmetics. This paper describes an actual implementation of the DSP architecture on a field programmable gate array (FPGA) platform. Some signal processing quality evaluation results are also presented for two audio applications that are realized on the DSP architecture.

Fast Affine Projection Algorithm using the Successive Over-Relaxation Method

Abstract: In this paper the implementation of several fast affine projection (FAP) algorithms using the Logarithmic Number system (LNS) is investigated. A new stable FAP algorithm based on Successive Over-Relaxation (SORFAP) method is proposed. Also, a simplified version of SORFAP algorithm is investigated. We show that the 32-bit or 20-bit LNS implementation of the SORFAP algorithm is simpler than that of other FAP algorithms and easy to implement on FPGA or DSP. It is only marginally complex than NLMS and is a better alternative to NLMS algorithm in different voice applications.