Showing papers on "Logarithmic number system published in 2018"

Logarithmic number system for deep learning

Abstract: In this paper the logarithmic Number System (LNS) is adopted to implement Long-Short Term Memory (LSTM), the basic component of a deep learning network type. Initially, piece wise approximations to activation functions σ and tanh are proposed and evaluated in LNS. Secondly, LNS multipliers and adders are implemented for wordlengths of 9,10 and 11 bits. The circuits are implemented in an 90-nm 1.0 V CMOS standard-cell library and quantitative results are reported. Results demonstrate that LNS is a good candidate for data representation and processing in deep learning networks, as area reduction of up to 36% is possible.

RNA: An Accurate Residual Network Accelerator for Quantized and Reconstructed Deep Neural Networks

Abstract: With the continuous refinement of Deep Neural Networks (DNNs), a series of deep and complex networks such as Residual Networks (ResNets) show impressive prediction accuracy in image classification tasks. Unfortunately, the structural complexity and computational cost of residual networks make hardware implementation difficult. In this paper, we present the quantized and reconstructed deep neural network (QR-DNN) technique, which first inserts batch normalization (BN) layers in the network during training, and later removes them to facilitate efficient hardware implementation. Moreover, an accurate and efficient residual network accelerator (RNA) is presented based on QR-DNN with batch-normalization-free structures and weights represented in a logarithmic number system. RNA employs a systolic array architecture to perform shift-and-accumulate operations instead of multiplication operations. QR-DNN is shown to achieve a 1% ~ 2% improvement in accuracy over existing techniques, and RNA over previous best fixed point accelerators. An FPGA implementation on a Xilinx Zynq XC7Z045 device achieves 804.03 GOPS, 104.15 FPS and 91.41% top-5accuracyfortheResNet-50benchmark, andstate-of-the-art results are also reported for AlexNet and VGG.

Design of fast logarithmic converters with high accuracy for digital camera application

Abstract: In this paper, fast logarithmic converters with high accuracy are proposed. In previous works, using logarithmic number system (LNS)—based units can help to reduce the computation efforts in delay and area for digital signal processing applications. Among these LNS-based units, shift-and-and based scheme is the most suitable for low-error approximation with reduced area and delay costs. Based on the shift-and-add schemes, by adopting our proposed coefficients capturing schemes, the converters could achieve fast logarithmic conversion with high accuracy and reduced area costs. Therefore, our proposed converters could be applied to boost up the overall performance in logarithmic number systems. Our proposed logarithmic converters are synthesized using TSMC 0.18 μm process technology. Simulation results show that our proposed logarithmic converters could outperform previously proposed shift-and-add methods in the literature. Our proposed fast logarithmic converters with high accuracy can be applied to digital signal processing and digital camera application.

The slide number format

Abstract: The Slide number format divides the real number line into connected sets. Compared to the unum format [3], there is no ubit, no infinity, and values are placed on a logarithmic scale with base 10. Formal definitions for Slides and intervals composed of Slide pairs are provided. The relative error is compared with that of single precision floats. The performance of conversions to and from human readable form is measured.

Residue Logarithmic Coprocessor for Mass Arithmetic Computations

Abstract: The work is aimed at solving the urgent problems of modern high-performance computing. The purpose of the study is to increase the speed, accuracy and reliability of mass arithmetic calculations. To achieve the goal, author’s methods of performing operations and transforming data in the prospective residue logarithmic number system are used. This numbering system makes it possible to unite the advantages of non-conventional number systems: a residue number system and a logarithmic number system. The subject of study is a parallel-pipelined coprocessor implementing the proposed calculation methods. The study was carried out using the theory of computer design and systems, methods and means of experimental analysis of computers and systems. As a result of the research and development new scientific and technical solutions are proposed that implement the proposed methods of data computation and coding. The proposed coprocessor has high speed, accuracy and reliability of processing of real operands in comparison with known analogs based on the floating-point positioning system.