Showing papers on "Master clock published in 1996"

Method and system for recording vehicle data relative to vehicle standard time

Abstract: A master clock on a truck maintains vehicle standard time for the purposes of monitoring and recording vehicle performance data throughout the vehicle. Vehicle performance data is stored for a predefined period of time in response to detecting predefined events. Instances of vehicle performance data is time stamped with vehicle standard time. The master vehicle clock can also maintain the local time displayed to the driver. In response to inputs from the driver, the difference between driver local time and vehicle standard time is computed and the updated local time is displayed to the driver.

Method and apparatus for clock synchronization across an isochronous bus by adjustment of frame clock rates

Abstract: A mechanism for adjusting the frame clock used by an audio DSP or other functional unit to transfer data to the rate at which data is transferred across an isochronous bus. According to one embodiment of the present invention, there is provided a mechanism for monitoring the level of data in a data buffer. The data are transferred to the buffer from the audio DSP, and then out the buffer across the isochronous bus, such as a Universal Serial bus. If the level in the buffer is too high, the audio DSP is filling the data buffer too quickly. If the data level in the buffer is too low, then the audio DSP is not providing the data quickly enough. The frame clock on the audio logic which is used to generate and transfer the data to the buffer is adjusted. Thus, if the level in the buffer is too high, the frame clock will be slowed; if the level in the buffer is too low, the rate of the frame clock will be increased. More particularly, there is provided a programmable clock divider which receives as input a master clock used by the audio DSP for computational purposes, and from which the frame clock is derived. Responsive to the level of data in the buffer, the programmable clock divider will adjust the rate of the frame clock.

A stereo multi-bit /spl Sigma//spl Delta/ D/A with asynchronous master-clock interface

Abstract: An oversampling DAC that generates low-jitter, synchronous and oversampled clock internally uses an on-chip digital phase-locked loop (DPLL) and a digital sample-rate converter to decouple the DAC conversion rate from the audio sample rate. This allows the DAC to be driven by an independent low-jitter clock source that minimizes jitter-induced amplitude errors. The DAC uses a second-order /spl Sigma//spl Delta/ modulator in combination with a 17-level quantizer to achieve greater than 110 dB theoretical SNR and reduced out-of-band noise relative to higher-order 1b modulators. The problem of severe element matching in multi-bit DACs is addressed by applying a data-directed scrambling technique on the thermometer-decoded modulator output that modulates DAC element mismatch errors out of band.

Integrated circuit memory devices having improved dual memory bank control capability and methods of operating same

Abstract: Integrated circuit memory devices having improved dual memory bank control include circuits therein for controlling at least one pair of memory banks (e.g., DRAM memory banks) using a single row address strobe (RAS) signal. Such memory devices include first and second banks of memory cells and a memory bank control circuit coupled thereto for selectively disposing the first and second banks of memory cells in active modes of operation during respective nonoverlapping time intervals, in response to first and second master clock signals. The first and second master clock signals are generated by a single master clock signal generator comprising a row address strobe buffer and a bank select buffer. The strobe buffer is responsive to a row address strobe signal and the bank select buffer is responsive to outputs from the strobe buffer and a bank select signal. The bank select buffer preferably generates the first and second master clock signals at first logic potentials (e.g., logic 1) during nonoverlapping time intervals and at second logic potentials (e.g., logic 0) during overlapping time intervals. In response to the master clock signals, the memory bank control circuit disposes the first bank of memory cells in an active mode of operation when the first master clock signal applied thereto has an amplitude equal to the first logic potential and disposes the second bank of memory cells in an active mode of operation when the second master clock signal applied thereto has an amplitude equal to the first logic potential.

Clock rate compensation for a low frequency slave device

Abstract: A slave device having clock rate compensation circuitry for low frequency operation. The slave device is coupled to a bus having a first operating frequency yet uses a slave clock signal having a frequency less than the first operating frequency. The slave device includes a bus clock driver circuit coupled to a bus clock interface for a bus clock signal. A slave controller state machine is clocked by the slave clock signal and accordingly operates at less than the first operating frequency. The clock rate compensation circuitry receives the bus clock signal, a data signal, and the slave clock signal, and synchronizes bus events for the state machine. The clock rate compensation circuitry also asynchronously begins a bus clock signal stretching period.

Test system including a local trigger signal generator for each of a plurality of test instruments

Abstract: A local trigger signal generator is provided for each of a plurality of test instruments in a test system. The disclosed test system includes a master clock generator that defines a start time t 0 and generates a periodic master clock signal characterized by a master clock oscillation frequency f mc and a corresponding period T mc . The master clock generator generates a clock network signal that is representative of the master clock signal and the start time t 0 . The system further includes a set of n test instruments TIN1, TIN2, . . . TINn. An ith one of the test instruments TINi includes a local clock receiver for receiving the clock network signal and defining therefrom a local start time t 0 i and for generating therefrom a local timestamp signal LTSSi, where the local timestamp signal LTSSi is representative of a number of time intervals having a length substantially equal to the period T mc occurring after the local start time t 0 i. The ith test instrument also stores one or more local trigger values and generates one or more local trigger signals LTGSi when the local timestamp signal LTSSi equals one or more of the local trigger values.

Processor chip having on-chip circuitry for generating a programmable external clock signal and for controlling data patterns

Abstract: Techniques for matching the speed of a microprocessor to potentially slower external system components. A master clock signal is communicated to a clock generator on the processor chip. The clock generator provides at least one external clock signal, which is communicated to various portions of the system. The clock generator includes programmable clock division circuitry that allows the external clock signal to be generated at any selected one of a plurality of fractions of the master clock frequency. The data pattern (the particular cycles in a sequence during which the processor outputs a data word as part of a multiple-data-word sequence) is programmable independently of the external clock programming.

Apparatus and method for automatically sequencing clocks in a data processing system when entering or leaving a low power state

Abstract: A clock acquisition subsystem for a data processing system has an interlocked clock multiplexer 100 for acquiring a clock source which is provided as clock signal 102 to the data processing system. Multiplexer 100 has at least two inputs 104 and 106 for clock source signals. Each clock source signal can be connected to one or more clock sources 710 and 720. Control register 730 specifies which clock source is to be selected by the multiplexer. The multiplexer has an interlocked synchronizer on each clock signal input so that when the multiplexer is switched, output clock signal 102 transitions cleanly from a first clock source to a second clock source without glitches or runt pulses. While the data processing system is in a deep sleep low power mode, wakeup logic 750 can provide wakeup signal 751 to power down select logic 740 which automatically selects secondary clock 720 until primary clock 710 is operational.

Digital mobile communication system and timing design method between various subsystems

Abstract: A digital mobile communication system wherein a master clock of a mobile communication system for offering audio or data service using a code division multiple access (CDMA) is set as a global positioning system (GPS) clock provided in a GPS and the interface and timing between various subsystems using the GPS clock and an exchanger are redesigned to achieve an exact timing schedule, and a timing design method between various subsystems. In order to maintain frequency and time synchronization between various subsystems in a CDMA system using an exchanger therefor, the respective subsystems are designed based on the clock supplied from a GPS, a hardware interconnection between the systems is designed based on the GPS clock to attain an exact timing, thereby achieving a fast and exact frame transmission.

Apparatus and method for providing multiple channel clock-data alignment

Abstract: An apparatus and method for aligning any number of multiple parallel channels of data signals according to a single clock is provided. The synchronization process is accomplished through the use of a First-In-First-Out (FIFO) principle and individual storage elements implementing the FIFO principle for each received data channel. Each channel's data signals are read into a corresponding storage element, maintained in order, and read out upon the assertion of read signals in synchronization with a designated single clock signal. The apparatus and method preferably uses indications of data ready to be read from a storage element implementing the FIFO principle and the presence of a master clock signal to activate the reading of the data from the corresponding storage element. Therefore, each data channel is fully aligned with the master clock signal. The clock-data alignment function may be implemented for a 100BASE-T4 receiver.

Clock distribution network utilizing local deskewing clock generator circuitry

Abstract: A clock signal distribution network for a high-speed microprocessor includes a clock synthesizer (30) coupled to receive an externally generated clock signal. The clock synthesizer (30) deskews the external clock to generate an internal clock signal, which is then distributed about the semiconductor die by a conductivity tree. A set of local deskewing clock generators (40 a-d) are coupled to branch interconnects (31, 33 a-b, 34 a-d) of the tree and function as a zero-delay buffers for driving proximally located circuitry.

Sound source chip having variable clock to optimize external memory access

Abstract: In a sound source apparatus, a central processing unit is integrated in a semiconductor chip and operates in response to a primary operating clock signal for creating a control message. A tone generating unit is integrated in the same semiconductor chip and operates in response to a secondary operating clock signal for generating a musical tone according to the control message. A master clock generator generates a master clock signal having a desired frequency selected from a plurality of frequencies. A mode changer designates one of a first mode and a second mode corresponding to different operating speeds. A clock generator is provided for variably frequency-dividing the master clock signal to generate the primary operating clock signal and the secondary operating clock signal. The clock generator is responsive to the mode changer for changing a frequency ratio of the primary operating clock signal to the secondary operating clock signal between the first mode and the second mode. An external memory is provided separately from the semiconductor chip for storing information required for generation of the musical tone. A memory controller is provided for allotting a primary time slot to the central processing unit and a secondary time slot to the tone generating unit such as to optimize access to the external memory shared by the central processing unit and the tone generating unit. A cache memory is provided to speed up operation of the central processing unit.

Asynchronous timing generator

Abstract: The asynchronous timing generator is comprised of a clock signal generator that generates a master clock signal. The master clock signal is used by a master clock counter to generate a bit clock. The master clock counter divides the master clock signal's frequency down to a lower frequency. Control signal information is extracted from the data stream's slot-framing to control the use of a predefined count value to a variable counter. The variable counter uses this lower frequency clock signal to generate the sub-bit count clock signal and slot bit numbers. These signals are generated in response to the control signals, coupled to the timer, indicating the different fields of the slot used to resynchronize data recovery in the received stream. In a preferred embodiment, the asynchronous timing generator is used in a communications transceiver device to permit resynchronization of received communications data.

Distributed source-destination synchronization using inband clock distribution

Abstract: This paper presents a new distributed methodology for source destination synchronization for interactive teleconferencing. The method is based on a reference clock, which is synthesized from a distributed global clock. The global clock is generated by periodically exchanging inband synchronization signals with neighboring nodes. The timing jitter achieved with this method can be arbitrarily close to the jitter obtained by the centralized synchronous methods which usually use an out-of-band, hard-wired reference clock. The global clock synchronization algorithm, used in this work, guarantees frequency locking of all the network nodes to the slowest clock in the system. As a result, the slowest clock can be used as an implicit reference clock for source-destination synchronization protocols, such as synchronous frequency encoding technique (SFET) and synchronous residual time stamp (SRTS). This inband synchronization method does not require the explicit knowledge of which clock is actually the slowest in the system. Therefore, if the slowest clock fails, then another clock on a different node will be the slowest, and the nodes will use it as a reference clock for the source-destination synchronization protocol. The existing out-of-band reference clock techniques do not have this strong fault tolerant property.

Time-of-day clock synchronization in commincations networks

Abstract: A system for service control and operations for a telecommunications network. In particular, an architecture and method for a service control and operations element system. The system communicates with a plurality of interconnected telecommunications network elements via a switching and signaling subsystem. The system provides and controls the functions of the telecommunications network, including a method of measuring delay between the time a customer dials a phone number of a called party and the time the customer hears a ringback tone indicating that the called party was alerted to the call, a method of synchronizing clocks located at individual network elements with a centralized time source, and a method of time-of-day clock surveillance.

Latch optimization in hardware logic emulation systems

Abstract: A method for optimizing a logical design for emulation. The present invention optimzes latch-based designs by transforming them into a flip-flop based circuit. The design is analyzed to determine whether any consecutive latches are clocked by the same clock signal. If consecutive latches are clocked by the same clock signal, for example, the same phase of the same master clock, a transparency condition exists. Transparent latches are transformed into either a flip-flop/buffer/multiplexer circuit or a buffer circuit depending upon whether the latch in the logic design has an enable input. If consecutive latches in a design are clocked by different clock signals, i.e., different phases of the master clock, no transparency condition exists. Non-transparent latches are transformed into a flip-flop.

Baseband simulator architecture for testing a radio frequency section of a mobile communications transceiver

Abstract: A baseband simulation system is disclosed for testing an RF subsystem of a communication device, such as a cellular telephone, cordless telephone, etc. A preferred embodiment has a computer connected to an interface card which in turn is connected to a baseband simulation subsystem. The baseband simulation subsystem is connected to the RF subsystem under test. The baseband simulation subsystem includes three ports: a timing and control (TAC) port, an IQ port, and general purpose input output (GPIO) port. The TAC port receives a master clock signal from an external source and generates plural clocks therefrom. The IQ and GPIO ports receives at least one of these plural clocks. In a transmit mode, in response to one or more of the clocks generated by the TAC port, the IQ port retrieves from its memory prestored discrete I and Q samples and reconstructs therefrom arbitrary transmit analog i and q signals which are provided to the RF subsystem under test. In a receive mode, the IQ port receives analog i and q signals from the RF subsystem. The IQ port, in response to one or more clocks generated by the TAC port, converts the received analog i and q signals receive discrete I and Q samples. These receive discrete I and Q samples are transferred via the PCIF to the PC for analyzing the ability of the RF subsystem under test to modulate the inputted transmit analog i and q signals on one or more RF carrier signals and to demodulate the RF carrier signals to output the receive analog i and q signals. The GPIO port exchanges auxiliary discrete data with the PC and auxiliary analog signals with the RF subsystem under test.

Synchronous stress test control

Abstract: The present invention ensures that the entire data path of the synchronous integrated circuit device composed of master and slave latches is initialized upon power-up in a test mode, thereby overcoming a prior art problem of non-initialization of the device data path. In the test mode, the master clock signal is initialized internally to the synchronous integrated circuit device to allow the master latch to conduct. A clock signal which is a derivative of a master clock signal is controlled to be equal to a first logic state in order to control a slave latch element of the synchronous integrated circuit device to conduct, regardless of the state of the master clock signal. Controlling the clock signal to be equal to the first logic state allows the clock signal to be able to control the slave latch element so that entire data path of the integrated circuit device is initialized upon power-up of the device in the test mode. The logic state of the clock signal is controlled by a clock control circuit which sets the logic state of the clock as a function of whether the device is in a test mode. Thus, the master clock signal which controls the master latch element and the clock signal which controls the slave latch element are controlled such that the master latch and the slave latch conduct simultaneously for proper and full initialization of the device data path upon power-up of the device in a test mode.

Phase linking of output clock with master clock in memory architecture

Abstract: An independent and cooperative memory architecture is provided which includes a plurality of multi-line channels each capable of carrying either data or address information to a plurality of independent memory clusters. The memory architecture includes a slave port for shifting the burden of scheduling and synchronization from a master device to a memory device. By coupling the master device's clock signal to a counter and to an enabler coupled to a FIFO, the slave port makes it possible for the master device to request data from the memory device and to begin clocking out the requested data from the slave port after a fixed number of clock cycles of the master device's clock. The slave port guarantees that data from the memory device is available to the master device following an output access time of the memory device.

Redundancy clock supply module for exchange system

Abstract: An exchange system comprising a plurality of redundant clock supply modules for receiving respective clock signals to maintain synchronization. Each redundant clock supply module includes a phase locked loop coupled to receive a network synchronizing reference signal, for generating a most significant clock of the exchange system synchronized to the network synchronizing reference signal; a clock generator for counting the most significant clock to generate a plurality of system clocks including a least significant clock and a first frame pulse; and a redundancy synchronizer for synchronizing the first frame pulse and a second frame pulse from a counterpart redundancy module to generate a redundancy synchronization signal for establishing synchronization between redundancy modules from the most significant clock to the least significant clock.

Programmable multiple CCD clock synthesizer

Abstract: The clock synthesizer includes an oscillator section for providing a train of pulses corresponding to the transitions of a master clock signal, a first register coupled to the oscillator for dividing the train of pulses by a fixed integer to produce a plurality of first phase shifted signals corresponding in number to said integer, and a plurality of second shift registers corresponding in number to the integer and each having a clocking input coupled to a respective one of the first phase shifted signals. The second registers produce a plurality of second phase shifted signals having leading edge transitions separated from each other by displacements corresponding to the transitions of the master clock signal. The second phase shifted signals are then combined to generate the lower frequency clock pulses, which may be used, e.g., in the clocking of a charge coupled device image sensor.

Synchronization clock distribution system for synchronization transmission system

Abstract: PROBLEM TO BE SOLVED: To warrant phase synchronization among plural synchronization transmitters even on the occurrence of a fault in any of synchronization clock distribution lines with redundant configuration. SOLUTION: Ring distribution lines R0, R1 for 0 system/1 system synchronizing clocks CK0, CK1 are formed by interconnecting a distributed clock system(DCS) 1 and synchronization transmitters 21-2n by distribution lines L00-L0n and L10-L1n respectively as rings. Each of the synchronization transmitters 21-2n relays respectively the 0 system/1 system synchronizing clocks CK0, CK1 but stops a synchronizing clock to be outputted to a succeeding transmitter upon the detection of a fault in the synchronizing clock being received. Thus, on the occurrence of a fault anywhere in the distribution lines L00-L0n and L10-L1n, the synchronizing clock to be returned to the DCS 1 is missing. The DCS 1 receives/monitors the synchronizing clocks CK0, CK1 outputted by itself and in the case of detecting clock missing, the DCS 1 stops output of the missing synchronizing clock. COPYRIGHT: (C)1997,JPO

Clock for a fail-fast, fail-functional, fault-tolerant multiprocessor system

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The system comprises apparatus for providing synchronized clock signals to at least a pair of synchronous processing elements, where each of the pair of processing elements includes a master oscillator circuit to produce a master clock signal, a clock generator circuit coupled to receive the master clock signal to produce the synchronized clock signals therefrom, the clock generator circuit having a voltage controlled oscillator circuit responsive to a phase voltage to produce a first clock signal, a counter circuit coupled to receive the first clock signal produce a number of divisions of the first clock signal forming the synchronized clock signals and a replica of the master clock signal, and a phase compare means coupled to receive the master clock signal and the replica of the master clock signal to produce the phase voltage; and means for coupling the master oscillator circuit of a one of the pair of processing elements to provide the master clock signal for the clock generator to the pair of processing elements.

Electronic digital clock distribution system

Abstract: More particularly, an electronic digital clock distribution system provides a plurality of working rank clock signals to respective ones of a plurality of logic circuits. Each clock signal has a predetermined frequency and each logic circuit requires a working rank clock signal having a predetermined level of electrical power. An oscillator produces a master clock signal at the predetermined frequency and at an electrical power level at least equal to the sum of the power requirements for all working rank clock signals of the plurality of logic circuits. An electronic splitter network is connected to the oscillator to splitting the master clock signal into the plurality of working rank clock signals.

Circuit and method for generating non-overlapping clock signals for an integrated circuit

Abstract: A method is provided for forming non-overlapping clock signals 402 and 404 for an integrated circuit. A reference clock 300 whose frequency is twice that of a desired operating frequency for the integrated circuit is used. A master clock signal is formed which has a high pulse width T9a which is approximately the same as the high pulse width of the reference clock, but the frequency of the master clock is one half the frequency of the reference clock. Likewise, a slave clock signal is formed which has a high pulse width T10a which is approximately the same as the high pulse width of the reference clock, but the frequency of the slave clock is also one half the frequency of the reference clock. The high pulse width of either or both the master clock signal and slave clock signal is then widened by an analog delay means, but by an amount T13 and T14 which is less than the low pulse width of the reference clock, so that the master clock signal and the slave clock signal do not overlap each other. As the propagation time of circuit elements within the integrated circuit varies due to changes in operating temperature or voltage, the analog delay T13 and T14 is changed proportionally to compensate for the changes in propagation time of the circuit elements.

Continuous Observation of Navstar Clock Offset from the DoD Master Clock Using Linked Common-View Time Transfer

Abstract: : Analysis of the on-orbit Navstar clocks and of the Global Positioning System (GPS) and National Imaging and Mapping Agency (NIMA) monitor station reference clocks is performed by the Naval Research Laboratory (NRL) using both broadcast and postprocessed precise ephemerides. The precise ephemerides are produced by NIMA for each of the GPS space vehicles from pseudorange measurements collected at five GPS and seven NIMA monitor stations spaced around the world. That the time reference for the NIMA Washington, DC, monitor station is the DoD Master Clock has enabled synchronized time transfer every 15 minutes via Linked Common-View Time Transfer from the DoD Master Clock to the eleven monitor stations. Summing the offset of a space vehicle clock from a monitor station time reference with the offset of the monitor station time reference from the DoD Master Clock yields the offset of the space vehicle clock from the Master Clock for the period during which the space vehicle was in view of the monitor station. Repeating this procedure for each of the monitor stations produces continuous overlapping observations of the offset of the Navstar clock from the DoD Master Clock. Following this procedure for the Navstar 29 cesium clock for 118 days during which there were no anomalies in either the space vehicle clock or the Washington, DC monitor station time reference yielded a measurement noise with a standard deviation of 1.1 nanoseconds. This was reduced to an estimated measurement precision of 641 picoseconds by averaging overlapping measurements from multiple monitor stations at each observation time. Analysis of the low-noise clock offset from the DoD Master Clock yields not only the bias in time of the space vehicle clock, but focuses attention on structure in the behavior of the space vehicle clock not previously observable.

(abstract) Precision Time and Frequency Transfer Utilizing SONET OC-3

Abstract: An innovative method of distributing precise time and reference frequency to users located several kilometers from a frequency standard and master clock has been developed by the Timing Solutions Corporation of Boulder, CO. The Optical Two-Way Time Transfer System (OTWTTS) utilizes a commercial SONET OC-3 facility interface to physically connect a master unit to multiple slave units at remote locations. Optical fiber is a viable alternative to standard copper cable and microwave transmission. This paper discusses measurements of frequency and timing stability over the OTWTTS.

Device useful as a master/slave clock for transmitting standard time over a telephone network and a telephone network incorporating the device for transmitting and receiving standard time

Abstract: A device capable of transmitting or receiving time data in the master clock or slave clock modes respectively over standard telephone networks is a microprocessor based system with an independent clock and a time display unit. In the slave clock mode, the device can automatically dial the master clock to have its time corrected.