Showing papers on "Parasitic element published in 1980"

The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI

Abstract: Circuit requirements of scaled devices based on noise margin, parameter variation, parasitic resistance and drift velocity saturation lead to non-constant field scaling, which predict a maximum in performance as devices are scaled. This maximum occurs at a smaller length for p-channel than for n-channel for a given scaling rule, and causes the performance of the two to approach each other at L<0.3µm. The p-channel devices under these conditions are shown to be 100x less effected by hot carriers induced reliability problems than n-channel devices.

Semiconductor capacitance element

Abstract: PURPOSE:To eliminate the effect of parasitic resistance, by providing a connecting unit in a semiconductor well and in a polycrystalline semiconductor layer at positions where these are divided into resistance regions and connecting them electrically. CONSTITUTION:Polycrystalline Si layer 6 is provided with connecting unit 8' by means of Al wiring so as to divide the sheet resistance by opening a window on the protective film. P well is provided with diffusion layer 4', and on top of this is provided connecting unit 9' by means of Al wiring so as to divide the diffusion resistance. By this structure, the effect of parasitic resistance on the capacitance element used for high-frequency oscillation can be eliminated. It is effective when the distances between MOS gate and source and drain, used as capacitance element, are made short as much as possible and equal.

Voltage controlled UHF transistor oscillator - has octave range output using varicap diode and resonant line in base circuit with impedance shunt across diode removing parasitic resonance

Abstract: The oscillator consists of a transistor (2) whose transition frequency is greater than twice the maximum oscillator frequency The transistor is connected in common collector mode with a resonant circuit coupled to its base by a capacitor (19) The resonant circuit is a section of line (1) of predetermined characteristic impedance connected at one end to the transistor and at the other to a variable reactance formed by one or more varicap diode which is connected at its other end to ground The diode is shunted by a second section of line (24) of significantly higher impedance whose length is chosen inversely with the maximum operating frequency The diode serves to shift the effect of the parasitic inductance of the diode out of the operation band The varicap diode may be two diodes connected back to back so that they can be reverse biased despite the shunt The resonant lines and chokes of the circuit may be striplines formed by printed circuit techniques on a dielectric base, the other components being soldered in place The circuit uses low cost commercial components, and may be controlled to oscillate over the range 12 GHz to 23 GHz and may be used for down conversion of satellite broadcast TV without switched reactances

Fog clearing by microwave power

Abstract: A horn antenna for transmitting electromagnetic energy is combined with a parasitic element in coaxial, spaced relationship to define an annular aperture through which the energy is propagated. Radiation patterns occurring in the E and H planes of the antenna combination vary in response to both frequency of the energy and size of the parasitic element and combine to produce predetermined fields of radiation. Embodiments are disclosed which develop an outwardly diverging conical radiation pattern that is useful in fog clearing operations using a minimum of effective radiated power. Similar embodiments may be operated under swept frequency conditions to produce a continually changing radiation pattern that finds utility in radar systems.

Parasitic capacitance influence in micron and submicron CMOS/SOS

Abstract: The impact of parasitic capacitance in micron and submicron CMOS/SOS implementations is explored. Relative measures of parasitic fringing and interconnect capacitance associated with ring oscillator and high-speed 1/64 frequency divider (400 MHz at 4V) circuit layouts are investigated. Parasitic capacitance figures of merit are analyzed in terms of several key geometrical dimensions, from which sensitivity of parasitic influence on circuit speed to departure from ideal scaling laws can be deduced. Analytical and numerical results and design considerations moderating deleterious effects of parasitic capacitance in down scaling from 2 to 1 to 0.5µm CMOS/SOS technologies are discussed.

Gallium arsenide field effect transistor

Abstract: PURPOSE:To provide a Gallium Arsenide field effect transistor having excellent ultrahigh frequency characteristics by forming electrode wires of any of source, drain and multigates on a polyimide resin film to reduce parasitic element thereon CONSTITUTION:An n-type GaAs layer 2 and an n -type GaAs layer 2' are epitaxially formed in reduced thickness on a semiinsulating GaAs substrate 1, and mesa etched Then, Au-Ge and Ni layers are selectively formed to form ohmic electrodes 4, 5 thereon Thereafter, the layer 2' is selectively perforated with openings to form multigate electrode 3 of three layers of Ti-Mo-Au on the layer 2 A polyimide resin film 6 is coated thereon, openings are perforated on the necessary positions of the electrodes 3-5, Au/Mo/Ti layers 11 are coated on the entire surface Then, a resist mask 12 is provided to selectively electrically plate Au lead wires 7-9 and electrode 10 thereon The mast 12 and the metal layer 11 are etched to finally etch the substrate 1 to form the substrate 1 in desired predetermined thickness, and mesa etched to scribe the surface of the substrate to complete the field effect transistor According to this configuration it can reduce the parasitic capacity due to intersection of the electrode 10 and the electrodes 3, 4, and also reduce the value of parasitic elements without package

Highhfrequency field effect transistor

Abstract: PURPOSE:To avoid a drop of the gain in the high-frequency band by reducing the value of parasitic inductance by a method wherein when a source bias resistance element and a bypass capacitor element are connected to a high-frequency FET, these elements are incorporated in a package for the FET. CONSTITUTION:The metallic layer 10 for the drain electrode, which is made of metallized layer, is formed on the insulated substrate 9 of ceramics or the like, and the metallic layer 11 for the gate electrode is provided at a fixed interval from said layer 10. Also the metallic layers 12a, 12b for the source electrode, which are opposite to each other and orthogonal to said layers 10, 11, are formed, and the leads 14, 15, 16a, 16b are attached to those metallic layers 10, 11 12a, 12b to make up a package. After this, the FET chip 17 and the coupling body 13 on which the bias resistance element 22 and bypass capacitor element 23 are loaded are provided on the substrate 9 that is surrounded by the metal layers, and these are connected to the source electrode 18 on the chip 17 by means of the thin metal wires 19a, 19b.