P
Pallab K. Chatterjee
Researcher at Texas Instruments
Publications - 97
Citations - 2778
Pallab K. Chatterjee is an academic researcher from Texas Instruments. The author has contributed to research in topics: Transistor & Layer (electronics). The author has an hindex of 29, co-authored 97 publications receiving 2766 citations.
Papers
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Journal ArticleDOI
Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon
Satwinder Malhi,Hisashi Shichijo,Sanjay K. Banerjee,R. Sundaresan,M. Elahy,Gordon P. Pollack,William F. Richardson,Ashwin H. Shah,L.R. Hite,R.H. Womack,Pallab K. Chatterjee,H.W. Lam +11 more
TL;DR: In this paper, a design methodology was developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools.
Patent
Vertical DRAM cell and method
TL;DR: In this paper, a method for forming DRAM cells in pairs or quartets by excavating a trench or two trenches through the cell elements to split an original cell into two or four cells during fabrication is described.
Journal ArticleDOI
The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI
TL;DR: The p-channel devices under these conditions are shown to be 100x less effected by hot carriers induced reliability problems than the n-channel ones as mentioned in this paper, and the performance of the two to approach each other at L < 0.3µm.
Proceedings ArticleDOI
A trench transistor cross-point DRAM cell
William F. Richardson,D.M. Bordelon,Gordon P. Pollack,Ashwin H. Shah,Satwinder Malhi,Hisashi Shichijo,Sanjay K. Banerjee,M. Elahy,R.H. Womack,Chu-Ping Wang,James D. Gallia,H.E. Davis,Pallab K. Chatterjee +12 more
TL;DR: In this article, a 1T DRAM cell with both the transistor and the capacitor fabricated on the sidewalls of a deep trench is described, and its fabrication and characterization is discussed.
Patent
DRAM Cell with trench capacitor and vertical channel in substrate
TL;DR: In this paper, a dRAM cell and array of cells, together with a method of fabrication, was described, where the cell includes one field effect transistor and one storage capacitor with the capacitor formed in a trench in a substrate and the transistor channel formed by epitaxial growth on the substrate.