Showing papers on "Polycrystalline silicon published in 1969"

Igfet comprising n-type silicon substrate, silicon oxide gate insulator and p-type polycrystalline silicon gate electrode

Abstract: Insulated Gate Field Effect Transistor employing a polycrystalline semiconductor surface layer, one strip of which serves as the gate electrode of the IGFET, and another strip of which may serve as a resistor. The semiconductor surface layer is employed as a mask for the diffusion of the source and drain regions, thereby insuring automatic alignment between the gate electrode and the source and drain regions.

Dielectric isolated integrated circuit substrate processes

Abstract: Dielectric isolation has proven effective in raising inter-device breakdown voltages, lowering parasitic capacitances, and increasing resistance to radiation damage. The fabrication of a dielectric-isolated substrate, prior to diffusions, requires adequate control of the thickness of the epitaxial layer, of crowning and warpage, and of a necessarily smooth, damage-free surface. The mere juxtaposition of three or more layers of different materials, even before diffusion-induced strains, creates special problems because of coefficient-of-expansion mismatches. In addition, the substrates must pass through subsequent diffusion cycles and permit the fabrication of transistors with characteristics as good as (or better than) those made on p-n junction isolated substrates. There are three major methods of using silicon dioxide as a dielectric to separate active areas of an integrated circuit: 1) shape-back to the channels of a wafer which has had channels etched out and filled with polycrystalline silicon; 2) etch out and fill in with single crystal on an n+wafer which has already had isolation moats created; and 3) growth of polycrystalline silicon prior to etching the isolating channels. This paper describes and compares these methods.

Method of producing air-isolated integrated circuits

Abstract: Islands of dielectrically isolated monocrystalline silicon, fabricated in a polycrystalline base, are first produced. Device fabrication and beam lead interconnection follow. Thereafter the planar top surface is covered with an etch-resistant wax and the polycrystalline base is removed by etching. In another embodiment, SiO2 is grown on a grooved, monocrystalline silicon slice, and polycrystalline silicon is deposited thereover. The slice is then lapped down on the top side so that the polycrystalline silicon and SiO2 form barriers. Second side is lapped after devices are fabricated and after beam leads are formed. Active devices and beam leads are fabricated on one surface, and the polycrystalline material is lapped and etched away from the back. In either case, the remaining structure is an air-isolated beam lead device.

Monolithic integrated-circuit structure and method of fabrication

Abstract: Polycrystalline silicon having a needlelike oriented grain structure is found to have anisotropic electrical and thermal properties. A monolithic integrated-circuit structure having a plurality of monocrystalline silicon islands is fabricated in a polycrystalline silicon matrix having such a grain structure, with the grain direction oriented to provide maximum electrical resistivity between the monocrystalline islands, and maximum thermal conductivity toward a header or other heat sink. In one embodiment, the monocrystalline islands and polycrystalline matrix are grown by vapor deposition of silicon on a monocrystalline substrate provided with a suitable masking pattern, whereby the polycrystalline material grows on the mask concurrently with the growth of monocrystalline silicon on the unmasked areas of the substrate.