Showing papers on "Program counter published in 2020"

Implementation of 16-Bit Hack CPU on FPGA

Abstract: The design and implementation of a 16-Bit hack CPU, a modular processor, is presented in this paper The paper is intended to showcase the process involved in building a complex circuit capable of performing real-world computations, from the most basic component used for digital data representation that is the CMOS The design methodology used is a bottom-up approach, this starts with the construction of basic gates and moving up to major components like the program counter, ALU, etc and ends with the complete construction of the CPU using the previously built components in a modular manner This paper aims to give the reader a complete understanding of the functioning of a simple computer in a digital electronics abstract This paper will also give an idea about the data flow in a CPU triggered by a CPU An idea regarding the way a low-level programming language controls this data flow can also be understood This CPU design is easily implementable on an FPGA and is hence a great tool to teach students about the basics of Computer Architecture and Digital System Design The CPU reads instructions from the ROM and performs operations using the A register, D register, or the RAM units based on the instruction type There are mainly two types of instructions, instructions and C instructions The A instructions have the sole purpose of storing values into the A register while the C instruction can perform multiple operations

Design of an 8-bit Bit-Parallel RSFQ Microprocessor

Abstract: With Moore's law approaching its physical limits, low-temperature computing technology is ushering in unprecedented development opportunities. Rapid single-flux-quantum (RSFQ) circuit technology is currently the most mature superconducting integrated circuit technology. Based on the current fabrication process, we propose an 8-bit bit-parallel RSFQ microprocessor. The proposed microprocessor processes 8-bit data each clock cycle. Ten different instructions are executed. The microprocessor mainly consists of an on-chip instruction memory, two data registers, an instruction decoder, an 8-bit bit-parallel arithmetic logic unit, and a program counter. The microprocessor contains 7702 JJs (based on the Open Dataset of CONNECT Cell Library for AIST ADP2) without considering splitters, Josephson transmission lines, and passive transmission lines. We perform a logic-level simulation of the proposed microprocessor. The simulation results show correct operation with a target frequency of 16.7 GHz.

Out of Control: Reducing Probabilistic Models by Control-State Elimination.

Abstract: We present a new, simple technique to reduce state space sizes in probabilistic model checking when the input model is defined in a programming formalism like the PRISM modeling language. Similar in spirit to traditional compiler optimizations that try to summarize instruction sequences into shorter ones, our approach aims at computing the summary behavior of adjacent locations in the program's control-flow graph, thereby obtaining a program with fewer "control states". This reduction is immediately reflected in the program's operational semantics, enabling more efficient probabilistic model checking. A key insight is that in principle, each (combination of) program variable(s) with finite domain can play the role of the program counter that defines the flow structure. Unlike various reduction techniques, our approach is property-directed. In many cases, it suffices to compute the reduced program only once to analyze it for many different parameter configurations - a rather common workflow in probabilistic model checking. Experiments demonstrate that our simple technique yields a state-space reduction of about one order of magnitude on practically relevant benchmarks.

System and method for addressing data in memory

Abstract: The invention relates to a system and method for addressing data in a memory. The invention discloses a digital signal processor 100 with a CPU (110). The CPU has a program counter register (121) andoptionally an event context stack pointer register (122) for saving and recovering event handler context when higher priority events preempt lower priority event handlers. The CPU (110) is configuredto calculate an address for storing data in the memory (112, 114) using the minimized set of addressing patterns, including using the event context stack pointer register (122) and the program counterregister (121). The CPU (110) may also eliminate post-decrement addressing, pre-decrement addressing, and post-decrement addressing, and depend only on the post-decrement addressing.

Confidence and aggressiveness control of region prefetcher in computer memory

Abstract: The present disclosure relates to confidence and aggressiveness control of a region prefetcher in a computer memory, and provides a method of training a region prefetcher by receiving computer-executable instructions including a program counter and a data address. The method includes comparing a program counter of computer executable instructions with a storage table, the storage table including aprogram counter of anchor instructions and a corresponding offset vector representing a location of previously received offset accesses within a storage region defined by the anchor instructions. Inthe event that it is determined that the received computer executable instructions corresponds to one of the previously received offset accesses in the offset vector, the method determines whether thedata address of the computer executable instructions is accessed by a central processing unit. The storage table is modified by changing a value of at least one of a confidence level entry and a training level entry in the offset vector based on whether the central processing unit accesses the data address of the computer executable instructions.

Instruction processing method and chip

Abstract: Embodiment of this application provide an instruction processing method and a chip. The method is applied to the chip. The chip includes a thread unit and a search engine unit. The method includes: sending, by the thread unit, a search instruction to the search engine unit, where the search instruction includes a data address and a first search field, and the thread unit switches from a RUN state to a WAIT state; and receiving, by the thread unit, data and a program counter that are sent by the search engine unit, where the thread unit switches from the WAIT state to the RUN state. Because the thread unit needs to initiate only one search instruction to obtain the data and the program counter required by the thread unit. Therefore, the thread unit switches from the RUN state to the WAIT state only once, thereby reducing a quantity of times the thread unit switches to the WAIT state. In this way, an instruction processing process of the thread unit is accelerated, and core running efficiency of the chip and running efficiency of the chip are accelerated.

Indirect branch predictor security protection

Abstract: Techniques are disclosed relating to protecting branch prediction information In various embodiments, an integrated circuit includes branch prediction logic having a table that maintains a plurality of entries storing encrypted target address information for branch instructions The branch prediction logic is configured to receive machine context information for a branch instruction having a target address being predicted by the branch prediction logic, the machine context information including a program counter associated with the branch instruction The branch prediction logic is configured to use the machine context information to decrypt encrypted target address information stored in one of the plurality of entries identified based on the program counter In some embodiments, the branch prediction logic decrypts the encrypted target address information by performing a cipher to encrypt the machine context information and performing a Boolean exclusive-OR operation of the encrypted machine context information and the encrypted target address information

Methods, apparatuses, and media for processing loop instruction set

Abstract: The present disclosure provide a method, an apparatus, and a medium for processing a loop instruction set. The method includes: in response to obtaining a first start instruction of the loop instruction set, storing a first loop number related to the loop instruction set into a first register, and storing a value of a first program counter corresponding to a loop instruction following the first start instruction in the loop instruction set, into a second register. The method further includes: obtaining the loop instruction following the first start instruction in the loop instruction set for executing the loop instruction. The method further includes: in response to obtaining a first end instruction for indicating an end of the loop instruction set, determining a loop execution for the loop instruction set based on the first loop number and the value of the first program counter.

An apparatus and method for controlling a change in instruction set

Abstract: An apparatus and method are provided for controlling a change in instruction set. The apparatus has processing circuitry to execute instructions of an instruction set, with the processing circuitry being arranged to operate in a capability domain comprising capabilities used to constrain operations performed by the processing circuitry when executing the instructions. A program counter capability storage element is used to store a program counter capability used by the processing circuitry to determined a program counter value. The processing circuitry is arranged to employ a capability based mechanism to change the instruction set. In particular, in response to execution of at least one type of instruction that is used to load an identified capability into the program counter capability storage element, the processing circuitry is arranged to invoke the capability based mechanism in order to perform a capability check operation in respect of the identified capability, and to cause the instruction set to be identified by an instruction set identifier field from the identified capability provided the capability check operation is passed. This provides a controlled mechanism for allowing the instruction set to be changed, thereby alleviating the risk of inadvertent or malicious attempts to change the instruction set.

Control flow optimization in graphics processing unit

Abstract: Methodologies and architectures are provided for reducing control flow operations a graphics processing unit (GPU). In described embodiments, a GPU receives and compiles a conditional branch statement into a series of instructions including a branch instruction having an associated branch condition, an eject instruction, and an instruction with a merge indicator. Following execution of the branch instruction, the GPU executes the eject instruction, including modifying the entry of the divergence stack of the warp to include a target program counter value corresponding to the instruction with a merge indicator, and performing a bitwise complement operation on a current active mask to generate an updated active mask. In response to determining that all of the values of the updated active mask are false, the GPU sets the program counter to a program counter value corresponding to the instruction with a merge indicator.

Compound instruction set architecture for a neural inference chip

Abstract: A device for controlling neural inference processor cores is provided, including a compound instruction set architecture. The device comprises an instruction memory, which comprises a plurality of instructions for controlling a neural inference processor core. Each of the plurality of instructions comprises a control operation. The device further comprises a program counter. The device further comprises at least one loop counter register. The device is adapted to execute the plurality of instructions. Executing the plurality of instructions comprises: reading an instruction from the instruction memory based on a value of the program counter; updating the at least one loop counter register according to the control operation of the instruction; and updating the program counter according to the control operation of the instruction and a value of the at least one loop counter register.

System, apparatus and method for dynamic update to code stored in a read-only memory (ROM)

Abstract: In one embodiment, an apparatus includes: a control circuit to enable a comparison circuit based on a dynamic update to a hook table and a patch table; and the comparison circuit coupled to the control circuit to compare an address of a program counter to at least one address stored in the hook table, and in response to a match between the address of the program counter and the at least one address stored in the hook table, cause a jump from code stored in a read only memory to patch code stored in a patch storage. Other embodiments are described and claimed.

A Computational Design of a Programmable Biological Processor

Abstract: Basic synthetic information processing structures, such as logic gates, oscillators and flip-flops, have already been implemented in living organisms. Current implementations of these structures are, however, hardly scalable and are yet to be extended to more complex processing structures that would constitute a biological computer. Herein, we make a step forward towards the construction of a biological computer. We describe a model-based computational design of a biological processor, composed of an instruction memory containing a biological program, a program counter that is used to address this memory and a biological oscillator that triggers the execution of the next instruction in the memory. The described processor uses transcription and translation resources of the host cell to perform its operations and is able to sequentially execute a set of instructions written within the so-called instruction memory implemented with non-volatile DNA sequences. The addressing of the instruction memory is achieved with a biological implementation of the Johnson counter, which increases its state after an instruction is executed. We additionally describe the implementation of a biological compiler that compiles a sequence of human-readable instructions into ordinary differential equations-based models. These models can be used to simulate the dynamics of the proposed processor. The proposed implementation presents the first programmable biological processor that exploits cellular resources to execute the specified instructions. We demonstrate the application of the proposed processor on a set of simple yet scalable biological programs. Biological descriptions of these programs can be written manually or can be generated automatically with the employment of the provided compiler.

Instruction tightly-coupled memory and instruction cache access prediction

Abstract: Disclosed herein are systems and method for instruction tightly-coupled memory (iTIM) and instruction cache (iCache) access prediction. A processor may use a predictor to enable access to the iTIM or the iCache and a particular way (a memory structure) based on a location state and program counter value. The predictor may determine whether to stay in an enabled memory structure, move to and enable a different memory structure, or move to and enable both memory structures. Stay and move predictions may be based on whether a memory structure boundary crossing has occurred due to sequential instruction processing, branch or jump instruction processing, branch resolution, and cache miss processing. The program counter and a location state indicator may use feedback and be updated each instruction-fetch cycle to determine which memory structure(s) needs to be enabled for the next instruction fetch.

Circuitry and method

Abstract: Method and circuitry comprising data handling circuitry having memory (instruction cache 428 or branch prediction memory 134), which in primary mode performs data handling by accessing the memory, but in secondary mode, data handling function is independent of memory. Test circuitry (memory built-in self-test MBIST) controls a test operation during execution of a data set by a data processor which executes data processing instructions by reference to the data handling function. Test circuitry controls the data handling circuitry to transition from primary to secondary modes in response to initiation of the memory test, data processor then executes data set processing instructions by reference data handling function in secondary mode whilst memory is tested (simultaneous online testing); test circuitry also controls data handler to return to primary mode on completion of test. The data handler may comprise a branch predictor 132 to predict data processor’s next data processing instruction fetched. In primary mode branch predictor may predict fetched next data processing instruction based on stored history. In secondary mode, prediction may be based on input data selected from set instruction parameters and subsets of previous branch instruction data stored in registers relating to execution outcomes and predicting fetched instruction at target address (backward branch) or next program counter value 420 (forward branch). In the secondary mode the branch predictor may alternatively generate a fixed prediction (e.g BRANCH NOT TAKEN). Alternatively the memory may be instruction cache memory 428 and include a buffer 430 holding a set number of operations to modify cache memory content.