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Showing papers on "Programmable logic device published in 1969"



Patent
Dale C Gunderson1
23 May 1969
TL;DR: In this article, two and five separate memory cells per logic cell were used to provide a VARIETY of ELEMENTARY LOGIC FUNCTIONS, and the states of the MEMORY CELLs can be CHANGED or programmed to PROVIDE a variety of educational programs.
Abstract: THIS DISCLOSURE SHOWS TWO EMBODIMENTS F A LOGIC CELL USING TWO AND FIVE BISTABLE MEMORY CELLS PER LOGIC CELL. THE STATES OF THE MEMORY CELLS CAN BE CHANGED OR PROGRAMMED TO PROVIDE A VARIETY OF ELEMENTARY LOGIC FUNCTIONS.

6 citations


Patent
22 Jul 1969
TL;DR: In this paper, a thin film programmable configuration that can be programmed to function either as an AND or an OR gate is presented, and the arrangement of a plurality of these logic structures into a matrix configuration is accomplished by the use of thin film technology.
Abstract: Performance of logic functions disclosed is accomplished by a thin film programmable configuration that can be programmed to function either as an AND or an OR gate The arrangement of a plurality of these logic structures into a matrix configuration is accomplished by the use of a thin film technology The very simple basic thin film logic device is not restricted to use in a matrix configuration but, may be used in any suitable configuration or manner that is especially adaptable to thin film construction

3 citations


01 May 1969
TL;DR: A new type of fixed-cell, fixed-interconnection homogene cellular array that is capable of realizing any n-input, n-output combinational switching network is developed.
Abstract: : A new type of fixed-cell, fixed-interconnection homogene cellular array that is capable of realizing any n-input, n-output combinational switching network is developed. The array is composed of identical combinational logic cells with three inputs and three outputs. The logic cells are arranged in a rectangular array with uniform interconnection structure. The signal flow is unilateral in vertical direction and bilateral in horizontal direction. Each n-column array is capable of realizing any set of n functions of n variables. The functional capabilities of the array can be changed by appropriately setting the parameters on the edges of the array. An algorithm for the realization of any given 2n-state sequential machine by using a single n-column array is presented. The theoretical work that leads to the synthesis of this array is also presented. (Author)

1 citations


Proceedings ArticleDOI
H. Gold1, R. Pedersen
01 Jan 1969
TL;DR: The basic gate design and performance of a multi-chip logic circuit will be discussed and subnanosecond propagation delays in a system environment have been achieved using beam-lead silicon integrated-circuit chips assembled on ceramic substrates.
Abstract: Subnanosecond propagation delays in a system environment have been achieved using beam-lead silicon integrated-circuit chips assembled on ceramic substrates. The basic gate design and performance of a multi-chip logic circuit will be discussed.

Journal ArticleDOI
TL;DR: Yau and Tang address themselves to the problem of designing complex logical building blocks that determine the terminal control signal sets in the programmable logic arrays.
Abstract: The integrated circuit technology is still in the process of growth and evolution. The full impact of this technology on future logical design methods is yet to come. At this point one can only wonder whether the future digital circuits will be designed in the form of strictly cellular arrays or in the form of IC circuit packages of standard "cell types" with customized metallization interconnection, or a hybrid combination of these together with cellular or noncellular "programmable logic arrays." Whatever might be the form, it seems rather certain that a basic problem common to all these approaches is the problem of designing complex logical building blocks. These blocks become the basic cells of the cellular arrays, the basic "functional units" for the customized interconnection schemes, and determine the terminal control signal sets in the programmable logic arrays. Yau and Tang have addressed themselves to this important problem without specifically stating these motivations in their paper.